| Patent Number |
Title Of Patent |
Date Issued |
| 7612430 |
Silicon bipolar transistor, circuit arrangement and method for producing a silicon bipolar trans |
November 3, 2009 |
| The silicon bipolar transistor (100) comprises a base, with a first highly-doped base layer (105) and a second poorly-doped base layer (106) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer (106). |
| 7234237 |
Method for producing a protective cover for a device |
June 26, 2007 |
| In a method for producing a protective cover for a device formed in a substrate, at first a sacrificial structure is produced on the substrate, wherein the sacrificial structure comprises a first portion covering a first area of the substrate including the device and a second portion |
| 7135757 |
Bipolar transistor |
November 14, 2006 |
| A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The |
| 7064360 |
Bipolar transistor and method for fabricating it |
June 20, 2006 |
| A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low te |
| 6909141 |
Method for producing a vertical semiconductor transistor component and vertical semiconductor tr |
June 21, 2005 |
| A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on |
| 6903454 |
Contact spring configuration for contacting a semiconductor wafer and method for producing a con |
June 7, 2005 |
| A contact spring configuration for contacting semiconductor wafers is provided. At least one strip-type contact spring is provided on a substrate. The contact spring is fixed to a surface of the substrate on one side and is composed of a semiconductor material having a stress gradien |
| 6878600 |
Method for fabricating trench capacitors and semiconductor device with trench capacitors |
April 12, 2005 |
| A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance th |
| 6867105 |
Bipolar transistor and method of fabricating a bipolar transistor |
March 15, 2005 |
| A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The |
| 6863769 |
Configuration and method for making contact with the back surface of a semiconductor substrate |
March 8, 2005 |
| A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance |
| 6746880 |
Method for making electrical contact with a rear side of a semiconductor substrate during its pr |
June 8, 2004 |
| A method for electrically contacting a rear side of a semiconductor substrate when processing the semiconductor substrate includes the step of placing the semiconductor substrate with a substrate rear side on a substrate holder such that an electrically conductive contact layer formed |
| 6635545 |
Method for fabricating a bipolar transistor and method for fabricating an integrated circuit con |
October 21, 2003 |
| The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a c |
| 6552385 |
DRAM memory capacitor having three-layer dielectric, and method for its production |
April 22, 2003 |
| A DRAM capacitor is described that contains a BaSrTiO.sub.3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped. |
| 6548846 |
Storage capacitor for a DRAM |
April 15, 2003 |
| A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is |
| 6215140 |
Electrically programmable non-volatile memory cell configuration |
April 10, 2001 |
| A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls o |
| 6204119 |
Manufacturing method for a capacitor in an integrated memory circuit |
March 20, 2001 |
| A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material |
| 6197666 |
Method for the fabrication of a doped silicon layer |
March 6, 2001 |
| A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH.sub.4, Si.sub.2 H.sub.6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a co |
| 6194765 |
Integrated electrical circuit having at least one memory cell and method for fabricating it |
February 27, 2001 |
| An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two |
| 6159815 |
Method of producing a MOS transistor |
December 12, 2000 |
| In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective |
| 6140177 |
Process of forming a semiconductor capacitor including forming a hemispherical grain statistical |
October 31, 2000 |
| For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective |
| 6133126 |
Method for fabricating a dopant region |
October 17, 2000 |
| A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulatin |
| 6127220 |
Manufacturing method for a capacitor in an integrated storage circuit |
October 3, 2000 |
| On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so th |
| 6117790 |
Method for fabricating a capacitor for a semiconductor memory configuration |
September 12, 2000 |
| A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive laye |
| 6040995 |
Method of operating a storage cell arrangement |
March 21, 2000 |
| For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide laye |
| 5817553 |
Process for manufacturing capacitors in a solid state configuration |
October 6, 1998 |
| Capacitors, in particular stacked capacitors for a dynamic memory cell configuration are manufactured by first forming a sequence of layers, which include layers made of a first conductive material alternating with layers made of a second material. The second material can be selectively |
