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Inventor:
Franaszek; Peter A.
Address:
Katonah, NY
No. of patents:
13
Patents:












Patent Number Title Of Patent Date Issued
5345228 Very large scale modular switch September 6, 1994
Switch resources for a one-sided crosspoint switch with distributed control (i.e., switch ports, internal busses and controllers) have been organized so that modular growth is facilitated by: (1) assigning each switch port uniquely to one of the controllers; (2) making each controller ha
5264842 Generalized usage of switch connections with wait chain November 23, 1993
Requestors for a busy port in a multi-port communication system are enqueued in wait chains. The connectivity of a crossbar switch is employed to store the wait chains. Elements of the wait chain are modified to provide the right connections; that is, a group of ports are connected by
5235592 Dynamic switch protocols on a shared medium network August 10, 1993
Dynamic switch protocols are implemented on a token bus protocol in a shared medium network to improve the basic token bus functional capabilities and link utilization, and to produce a uniform transaction protocol that supports both token bus and dynamic switch networks. Frame forma
5193188 Centralized and distributed wait depth limited concurrency control methods and apparatus March 9, 1993
A wait depth limited concurrency control method for use in a multi-user data processing environment restricts the depth of the waiting tree to a predetermined depth, taking into account the progress made by transactions in conflict resolution. In the preferred embodiment for a centralize
5107489 Switch and its protocol for making dynamic connections April 21, 1992
A dynamic switch and its protocol for establishing dynamic connections in a link by the use of frames, each frame having an identification of the source of the frame, an identification of the destination of the frame for the requested connection, and link controls to maintain, initiate o
5001730 Clock synchronization algorithm for address independent networks March 19, 1991
A distributed algorithm for clock synchronization in address independent networks such as token rings and token busses is described. Synchronization is accomplished by using the fastest clock in the network as the master clock against which all other clocks in the network are synchro
4984237 Multistage network with distributed pipelined control January 8, 1991
A multistage network having a combination of low latency and probability of blockage has particular application in the interconnection of parallel computers. A technique minimizes the blockage of the multistage network, thereby minimizing the number of times that a message requires r
4929940 Collision crossbar switch May 29, 1990
A high speed collision N.times.M tri-state crossbar switch having M collision busses uses contention detection at the destination. In the event of a collision of messages, remedial action can be taken such as rerouting colliding messages over an alternate path provided by a second in
4763122 Parallel switching with round robin priority August 9, 1988
An apparatus for parallel control of access of a number of stations to a transmission line. More specifically, this invention uses a transmission loop which intercouples a number of switches. Some of these switches, station switches, are used to indicate that a station has a request for
4609907 Dual channel partial response system September 2, 1986
Method and apparatus is described for encoding and decoding a stream of randomly distributed binary bits representing digital data, including an encoder for encoding the bit stream to achieve a run length limited, partial response coding of the stream; a recording medium for recording
4525724 Magnetic recording head array for longitudinal magnetic printing with staggered head arrangement June 25, 1985
A magnetic recording head array for printing onto a transfer magnetic recording medium which prints magnetic material onto a medium such as paper includes staggered arrays of magnetic print heads. The heads are in diagonally staggered parallel arrays tilted away from the vertical. Each
4488142 Apparatus for encoding unconstrained data onto a (1,7) format with rate 2/3 December 11, 1984
An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequentia
4486739 Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code December 4, 1984
A binary DC balanced code and an encoder circuit for effecting same is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of t










 
 
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