| Patent Number |
Title Of Patent |
Date Issued |
| 7620921 |
IC chip at-functional-speed testing with process coverage evaluation |
November 17, 2009 |
| Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust |
| 7555740 |
Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corne |
June 30, 2009 |
| Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated ci |
| 7444608 |
Method and system for evaluating timing in an integrated circuit |
October 28, 2008 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
| 7401307 |
Slack sensitivity to parameter variation based timing analysis |
July 15, 2008 |
| A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on eac |
| 7181711 |
Prioritizing of nets for coupled noise analysis |
February 20, 2007 |
| A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack |
| 7089143 |
Method and system for evaluating timing in an integrated circuit |
August 8, 2006 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
