| Patent Number |
Title Of Patent |
Date Issued |
| 7550824 |
Low k interconnect dielectric using surface transformation |
June 23, 2009 |
| Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement |
| 7535103 |
Structures and methods to enhance copper metallization |
May 19, 2009 |
| Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. T |
| 7411823 |
In-service reconfigurable DRAM and flash memory device |
August 12, 2008 |
| A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. |
| 7394157 |
Integrated circuit and seed layers |
July 1, 2008 |
| Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. |
| 7387912 |
Packaging of electronic chips with air-bridge structures |
June 17, 2008 |
| A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plural |
| 7378737 |
Structures and methods to enhance copper metallization |
May 27, 2008 |
| Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. T |
| 7359241 |
In-service reconfigurable DRAM and flash memory device |
April 15, 2008 |
| A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. |
| 7301190 |
Structures and methods to enhance copper metallization |
November 27, 2007 |
| Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. T |
| 7239025 |
Selective deposition of solder ball contacts |
July 3, 2007 |
| Methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball contacts using selective deposition of solder on metal contact pads of a device. The metal contact pads have exposed portions at |
| 7205229 |
Interconnect alloys and methods and apparatus using same |
April 17, 2007 |
| Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for improved coverage of high aspect ratio features with reduced deposition pressure. The alloys are used to fabricate intercon |
| 7190616 |
In-service reconfigurable DRAM and flash memory device |
March 13, 2007 |
| A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. |
| 7186664 |
Methods and structures for metal interconnections in integrated circuits |
March 6, 2007 |
| A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with |
| 7161246 |
Interconnect alloys and methods and apparatus using same |
January 9, 2007 |
| Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for improved coverage of high aspect ratio features with reduced deposition pressure. The alloys are used to fabricate intercon |
| 7132348 |
Low k interconnect dielectric using surface transformation |
November 7, 2006 |
| Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement |
| 7121919 |
Chemical mechanical polishing system and process |
October 17, 2006 |
| Chemical mechanical polishing (CMP) systems and methods are provided herein. One aspect of the present subject matter is a polishing system. One polishing system embodiment includes a platen adapted to receive a wafer, and a polishing pad drum that has a cylindrical, or generally cyl |
| 7105914 |
Integrated circuit and seed layers |
September 12, 2006 |
| Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. |
| 6979848 |
Memory system with conductive structures embedded in foamed insulator |
December 27, 2005 |
| A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded |
| 6946389 |
Method of forming buried conductors |
September 20, 2005 |
| Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive |
| 6943090 |
Aluminum-beryllium alloys for air bridges |
September 13, 2005 |
| A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improve |
| 6890847 |
Polynorbornene foam insulation for integrated circuits |
May 10, 2005 |
| Methods of providing foamed polynorbornene insulating material for use with an integrated circuit device, as well as apparatus and systems making use of such foamed polynorbornene insulating materials. The methods include forming a layer of polynorbornene material and converting at least |
| 6879017 |
Methods and structures for metal interconnections in integrated circuits |
April 12, 2005 |
| A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with |
| 6872671 |
Insulators for high density circuits |
March 29, 2005 |
| A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded |
| 6844253 |
Selective deposition of solder ball contacts |
January 18, 2005 |
| Methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball contacts using selective deposition of solder on metal contact pads of a device. The metal contact pads have exposed portions at |
| 6838764 |
Insulators for high density circuits |
January 4, 2005 |
| A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded |
| 6784550 |
Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication |
August 31, 2004 |
| A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contain |
| 6780721 |
Low dielectric constant shallow trench isolation |
August 24, 2004 |
| Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon |
| 6774035 |
Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication |
August 10, 2004 |
| A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contain |
| 6770537 |
Low dielectric constant shallow trench isolation |
August 3, 2004 |
| Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon |
| 6756653 |
Low dielectric constant shallow trench isolation |
June 29, 2004 |
| Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to t |
| 6743716 |
Structures and methods to enhance copper metallization |
June 1, 2004 |
| Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. T |
| 6737723 |
Low dielectric constant shallow trench isolation |
May 18, 2004 |
| Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to t |
| 6717191 |
Aluminum-beryllium alloys for air bridges |
April 6, 2004 |
| A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improve |
| 6714445 |
Three terminal magnetic random access memory |
March 30, 2004 |
| Three terminal magnetic random access memory structures and methods. One aspect is a memory cell. One embodiment of the memory cell includes a first conductor line, a second conductor line, a third conductor line, and a magnetic storage element. The magnetic storage element is operably |
| 6696746 |
Buried conductors |
February 24, 2004 |
| Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive |
| 6614099 |
Copper metallurgy in integrated circuits |
September 2, 2003 |
| A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are less attractive than copper wires and polymer-based insulation, which promise |
| 6614092 |
Microelectronic device package with conductive elements and associated method of manufacture |
September 2, 2003 |
| A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device feat |
| 6552432 |
Mask on a polymer having an opening width less than that of the opening in the polymer |
April 22, 2003 |
| A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with |
| 6541859 |
Methods and structures for silver interconnections in integrated circuits |
April 1, 2003 |
| A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches wit |
| 6541858 |
Interconnect alloys and methods and apparatus using same |
April 1, 2003 |
| Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for improved coverage of high aspect ratio features with reduced deposition pressure. The alloys are used to fabricate interconnect |
| 6510080 |
Three terminal magnetic random access memory |
January 21, 2003 |
| Three terminal magnetic random access memory structures and methods. One aspect is a memory cell. One embodiment of the memory cell includes a first conductor line, a second conductor line, a third conductor line, and a magnetic storage element. The magnetic storage element is operably |
| 6509590 |
Aluminum-beryllium alloys for air bridges |
January 21, 2003 |
| A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improve |
| 6504224 |
Methods and structures for metal interconnections in integrated circuits |
January 7, 2003 |
| A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with |
| 6456535 |
Dynamic flash memory cells with ultra thin tunnel oxides |
September 24, 2002 |
| Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel ox |
| 6420262 |
Structures and methods to enhance copper metallization |
July 16, 2002 |
| Structures and methods are described that inhibit atomic migration which otherwise creates an undesired capacitive-resistive effect arising from a relationship between a metallization layer and an insulator layer of a semiconductor structure. A layer of an inhibiting compound may be used |
| 6413827 |
Low dielectric constant shallow trench isolation |
July 2, 2002 |
| Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon |
| 6377156 |
High-Q inductive elements |
April 23, 2002 |
| A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor throug |
| 6376895 |
High-Q inductive elements |
April 23, 2002 |
| A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor throug |
| 6376370 |
Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process |
April 23, 2002 |
| Structures and methods are provided which improve performance in integrated circuits. The structures and methods include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the |
| 6316356 |
Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication |
November 13, 2001 |
| A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contain |
| 6297156 |
Method for enhanced filling of high aspect ratio dual damascene structures |
October 2, 2001 |
| An integrated circuit alloy is described which reduces the alloy melting temperature for improved coverage of high aspect ratio features with a reduced deposition pressure. The alloy is used to fabricate metal contacts and interconnects in integrated circuits, such as memory devices. The |
