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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Farnworth; Warren M.
Address:
Nampa, ID
No. of patents:
719
Patents:


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Patent Number Title Of Patent Date Issued
RE34794 Gull-wing zig-zag inline lead package having end-of-package anchoring pins November 22, 1994
A semiconductor package having a gull-wing, zig-zag, inline-lead configuration and end-of-package anchoring devices for rigidly affixing the package to a circuit board such that each lead is in compressibe contact with its associated mounting pad on the board. The anchoring devices o
D402638 Temporary package for semiconductor dice December 15, 1998
D401567 Temporary package for semiconductor dice November 24, 1998
D394844 Temporary package for semiconductor dice June 2, 1998
8569093 Microelectronic devices and methods for manufacturing microelectronic devices October 29, 2013
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a radiation sensitive component in and/or on a microelectronic device, placing a curable component in and/or on the microelectronic de
8291966 Microelectronic devices with improved heat dissipation and methods for cooling microelectronic d October 23, 2012
Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second
8268715 Multi-component integrated circuit contacts September 18, 2012
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated
8129847 Interconnect and method for mounting an electronic device to a substrate March 6, 2012
An interconnect for mounting an electronic device to a substrate includes a base layer between the electronic device and the substrate in electrical communication with integrated circuits on the electronic device, a phase change layer on the base layer made of a material which is liq
8129839 Electronic device package structures March 6, 2012
A sealing layer is provided on a surface of a substrate, such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed to form discrete co
8115269 Integrated circuit package having reduced interconnects February 14, 2012
A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate
8053279 Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpie November 8, 2011
Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart
7989022 Methods of processing substrates, electrostatic carriers for retaining substrates for processing August 2, 2011
A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive
7964971 Flexible column die interconnects and structures including same June 21, 2011
A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in
7960829 Support structure for use in thinning semiconductor substrates and for supporting thinned semico June 14, 2011
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to
7956443 Through-wafer interconnects for photoimager and memory wafers June 7, 2011
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and
7923298 Imager die package and methods of packaging an imager die on a temporary carrier April 12, 2011
Methods for fabricating an imager die package and resulting die packages are disclosed. An imager die packaging process may include dicing through a fabrication substrate comprising a plurality of imager die. Thereafter, known good die (KGD) qualified from the imager die are repopulated,
7918383 Methods for placing substrates in contact with molten solder April 5, 2011
Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder bath, a nozzle for producing a solder wave, and a jig for orienting a substrate in a substantially vertical orientation and placing
7880307 Semiconductor device including through-wafer interconnect structure February 1, 2011
Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may comprise a substrate having a first surface and a second, opposing surface, and a through-wafer interconnect extending into the f
7875529 Semiconductor devices January 25, 2011
Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer
7872332 Interconnect structures for stacked dies, including penetrating structures for through-silicon v January 18, 2011
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a
7871859 Vertical surface mount assembly and methods January 18, 2011
A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a por
7855140 Method of forming vias in semiconductor substrates and resulting structures December 21, 2010
Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the cond
7833881 Methods for fabricating semiconductor components and packaged semiconductor components November 16, 2010
Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between
7833832 Method of fabricating semiconductor components with through interconnects November 16, 2010
A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate contacts, and forming openings from a backside of the substrate aligned with the substrate contacts. The method can also include t
7833456 Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece November 16, 2010
Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece are disclosed. A method in accordance with one aspect includes placing a semiconductor workpiece and an encapsulant in a mold cavity and driving some of the encapsulant from the mold cavity to an ov
7829976 Microelectronic devices and methods for forming interconnects in microelectronic devices November 9, 2010
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate
7829385 Taped semiconductor device and method of manufacture November 9, 2010
Printed tape is used to form a leads on chip (LOC) ball grid array (BGA) semiconductor device. Leads for a plurality of devices may be applied simultaneously. Bond wires, glob top encapsulant, and the ball grid arrays for the devices may be formed in single process steps. A low tempe
7807505 Methods for wafer-level packaging of microfeature devices and microfeature devices formed using October 5, 2010
Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known
7791184 Image sensor packages and frame structure thereof September 7, 2010
A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment.
7776647 Semiconductor components and methods of fabrication with circuit side contacts, conductive vias August 17, 2010
A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts on a circuit side of the substrate, conductive vias in electrical contact with the contacts, and conductors on a backside
7759240 Use of palladium in IC manufacturing with conductive polymer bump July 20, 2010
An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also
7730372 Device and method for testing integrated circuit dice in an integrated circuit module June 1, 2010
An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins,
7723741 Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-l May 25, 2010
Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can
7719120 Multi-component integrated circuit contacts May 18, 2010
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated
7713841 Methods for thinning semiconductor substrates that employ support structures formed on the subst May 11, 2010
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to
7709776 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i May 4, 2010
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external
7701039 Semiconductor devices and in-process semiconductor devices having conductor filled vias April 20, 2010
At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an ele
7683458 Through-wafer interconnects for photoimager and memory wafers March 23, 2010
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and
7674652 Methods of forming an integrated circuit package March 9, 2010
A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate
7663096 Microelectronic imaging devices and associated methods for attaching transmissive elements February 16, 2010
Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one embodiment of the invention includes providing an imager workpiece having multiple image sensor dies configured to detect energy ove
7649145 Compliant spring contact structures January 19, 2010
Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a silicon wafer or a carrier substrate is provided. At least one layer of a metal or alloy film may be deposited on the substrat
7645635 Frame structure and semiconductor attach process for use therewith for fabrication of image sens January 12, 2010
A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed i
7632713 Methods of packaging microelectronic imaging devices December 15, 2009
Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, the microelectronic imaging devices include an interposer substrate and a plurality of imager units coupled to the interposer substrate. The interposer su
7626269 Semiconductor constructions and assemblies, and electronic systems December 1, 2009
The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of
7603772 Methods of fabricating substrates including one or more conductive vias October 20, 2009
Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a
7600314 Methods for installing a plurality of circuit devices October 13, 2009
A technique is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a holder or shell. The holder is positioned over a support region in the receiving socket. A manual actuator is pressed into the
7598167 Method of forming vias in semiconductor substrates without damaging active regions thereof and r October 6, 2009
Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the semiconductor substrate unde
7594322 Methods of fabricating substrates including at least one conductive via September 29, 2009
A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. A
7591069 Methods of bonding solder balls to bond pads on a substrate, and bonding frames September 22, 2009
Methods and apparatuses for bonding solder balls to bond pads are described. In one embodiment, portions of a plurality of solder balls are placed within a frame and in registered alignment with individual bond pads over a substrate. While the ball portions are within the frame, the
7589010 Semiconductor devices with permanent polymer stencil and method for manufacturing the same September 15, 2009
Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.
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