| Patent Number |
Title Of Patent |
Date Issued |
| 7554374 |
Bounding a duty cycle using a C-element |
June 30, 2009 |
| A duty cycle bounding circuit for restoring the unbounded duty cycle of a periodic signal such as a forwarded clock signal. The duty cycle bounding circuit comprises a state holding logic element, such as a C-element, and a delay line. The delay line feeds back an inverted version of the |
| 6574690 |
Asynchronous pulse bifurcator circuit with a bifurcation path coupled to control fifo and first |
June 3, 2003 |
| A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a plurality of paths that exchange data between neighboring places. The bifurcator circuit generally comprises a control FIFO, two |
| 6486700 |
One-hot Muller C-elements and circuits using one-hot Muller C-elements |
November 26, 2002 |
| A one-hot Muller C-element, wherein an event received on each of a plurality of inputs results in an event being output, can be implemented with complementary inputs and a true transistor pair comprising one transistor having a gate coupled to a first true input and another transisto |
| 6456136 |
Method and apparatus for latching data within a digital system |
September 24, 2002 |
| A latching data system includes a memory element that is configured to store a data value. A latch input is coupled to the memory element, so that changes in the latch input change the data value stored in the memory element without waiting for an assertion of a clock signal. The system |
| 6420907 |
Method and apparatus for asynchronously controlling state information within a circuit |
July 16, 2002 |
| One embodiment of the present invention provides a system for asynchronously controlling state information within a circuit. This system includes a first conductor that carries a voltage indicating a state of the circuit, as well as a first drive circuit coupled to the first conducto |
| 6400230 |
Method and apparatus for generating and distributing a clock signal |
June 4, 2002 |
| One embodiment of the present invention provides a system that generates a clock signal within an integrated circuit. This system includes four clocking elements organized into a ring, wherein each clocking element includes at least one input and at least one output, and wherein a signal |
| 6356117 |
Asynchronously controlling data transfers within a circuit |
March 12, 2002 |
| One embodiment of the present invention provides a system for controlling asynchronous data transfers within a circuit. This system operates by monitoring a first voltage level on a first conductor that specifies whether a first stage of the circuit contains data. The system also mon |
| 6281707 |
Two-stage Muller C-element |
August 28, 2001 |
| A Muller C-element comprises two stages. The first stage consists of a NAND and a NOR gate, each driven by all of the inputs to the Muller C-element. In the second stage, the outputs of the two gates are used separately to switch on and off two output transistors, which drive the output |
| 6191658 |
High speed coupled oscillator topology |
February 20, 2001 |
| An oscillator circuit having a topology that provides for high-speed oscillation in an even number of phases. The topology generally comprises an even number of inverting circuit elements generally including a keeper and an even number of inverters. The circuit elements are connected suc |
| 6160438 |
Charge sharing selectors |
December 12, 2000 |
| The selector circuit rapidly steers an event from a single input to one of two outputs depending on the binary value of a data signal controlling the selector, where events are received at an event input. A selection value, placed at a control input causes the selector circuit to steer t |
| 6144226 |
Charge sharing selectors with added logic |
November 7, 2000 |
| The selector circuit rapidly steers an event from a single input to one of two outputs depending on the binary value of a data signal controlling the selector, where events are received at an event input. A selection value, placed at a control input causes the selector circuit to steer t |
| 6069514 |
Using asynchronous FIFO control rings for synchronous systems |
May 30, 2000 |
| A system for distributing clock signals to multiple locations on a chip with minimal skew is disclosed. A series of FIFO control structures, connected in a ring by signal lines of substantially equal length, generates multiple clock signals of equal phase and frequency. The oscillati |
| 5937177 |
Control structure for a high-speed asynchronous pipeline |
August 10, 1999 |
| Apparatus is disclosed for asynchronously controlling a pipeline. The control circuitry includes an alternating chain of control circuits and detection circuits. When a full control circuit precedes an empty control circuit in the chain, indicating that the data storage element corre |
