| Patent Number |
Title Of Patent |
Date Issued |
| 7519771 |
System and method for processing memory instructions using a forced order queue |
April 14, 2009 |
| A novel system and method for processing memory instructions. One embodiment of the invention provides a method for processing a memory instruction. In this embodiment, the method includes obtaining a memory request; storing the memory request in an Initial Request Queue (IRQ); and p |
| 7437521 |
Multistream processing memory-and barrier-synchronization method and apparatus |
October 14, 2008 |
| A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects of that relaxed memory |
| 7334110 |
Decoupled scalar/vector computer architecture system and method |
February 19, 2008 |
| In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit, a system and method of decoupling operation of the scalar processing unit from that of the vector processing unit, the method compris |
| 6665774 |
Vector and scalar data cache for a vector multiprocessor |
December 16, 2003 |
| A common scalar/vector data cache apparatus and method for a scalar/vector computer. One aspect of the present invention provides a computer system including a memory. The memory includes a plurality of sections. The computer system also includes a scalar/vector processor coupled to the |
| 6496902 |
Vector and scalar data cache for a vector multiprocessor |
December 17, 2002 |
| A common scalar/vector data cache apparatus and method for a scalar/vector computer. One aspect of the present invention provides a computer system including a memory. The memory includes a plurality of sections. The computer system also includes a scalar/vector processor coupled to the |
