| Patent Number |
Title Of Patent |
Date Issued |
| 6212639 |
Encryption of configuration stream |
April 3, 2001 |
| A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decryp |
| 6181158 |
Configuration logic to eliminate signal contention during reconfiguration |
January 30, 2001 |
| A structure for providing clearing/programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flo |
| 6100705 |
Method and structure for viewing static signal levels on integrated circuits using electron beam |
August 8, 2000 |
| A method and structure for testing static signal levels on an integrated circuit device using an electron beam deflection device. Each static signal is applied to a first terminal of a switch, such as an AND gate, an OR gate, or a pass transistor. An alternating control signal of app |
| 6057704 |
Partially reconfigurable FPGA and method of operating same |
May 2, 2000 |
| A field programmable gate array (FPGA) having an array of configuration memory cells arranged in rows and columns. The configuration memory cells store configuration data values for configuring the FPGA. Each configuration memory cell is coupled to a corresponding row line through a |
| 5995988 |
Configurable parallel and bit serial load apparatus |
November 30, 1999 |
| An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bit |
| 5990704 |
Internal drive circuit providing third input pin state |
November 23, 1999 |
| A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal wh |
| 5970142 |
Configuration stream encryption |
October 19, 1999 |
| A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decryp |
| 5969543 |
Input signal interface with independently controllable pull-up and pull-down circuitry |
October 19, 1999 |
| An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., |
| 5961576 |
Configurable parallel and bit serial load apparatus |
October 5, 1999 |
| An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bit |
| 5923614 |
Structure and method for reading blocks of data from selectable points in a memory device |
July 13, 1999 |
| A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, |
| 5920201 |
Circuit for testing pumped voltage gates in a programmable gate array |
July 6, 1999 |
| In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and |
| 5909453 |
Lookahead structure for fast scan testing |
June 1, 1999 |
| A scan lookahead skip structure that allows a programmable number of test bits, I/O blocks, flip-flops, or columns to be skipped. One embodiment of the structure includes multiplexers to skip the scan paths for several adjacent I/O blocks, flip-flops, or columns, thereby reducing the num |
| 5844829 |
Configurable parallel and bit serial load apparatus |
December 1, 1998 |
| An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bit |
| 5838167 |
Method and structure for loading data into several IC devices |
November 17, 1998 |
| An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. |
| 5815016 |
Phase-locked delay loop for clock correction |
September 29, 1998 |
| A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay |
| 5801546 |
Interconnect architecture for field programmable gate array using variable length conductors |
September 1, 1998 |
| An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output l |
| 5789938 |
Structure and method for reading blocks of data from selectable points in a memory device |
August 4, 1998 |
| A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, |
| 5770951 |
Configuration logic to eliminate signal contention during reconfiguration |
June 23, 1998 |
| A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programming the memory cells one set at a time, either in a first direction or a second direction. A struct |
| 5760607 |
System comprising field programmable gate array and intelligent memory |
June 2, 1998 |
| A memory device controls the flow of data from the memory device to a configurable logic device. This is in contrast to circuits in which a configurable logic device generates a clock signal that controls the flow of data from a memory device to a configurable logic device. In one em |
| 5760604 |
Interconnect architecture for field programmable gate array |
June 2, 1998 |
| An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output l |
| 5742531 |
Configurable parallel and bit serial load apparatus |
April 21, 1998 |
| An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bit |
| 5717340 |
Circuit for testing pumped voltage gates in a programmable gate array |
February 10, 1998 |
| In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and |
| 5694056 |
Fast pipeline frame full detector |
December 2, 1997 |
| A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified si |
| 5646564 |
Phase-locked delay loop for clock correction |
July 8, 1997 |
| A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. Th |
| 5640106 |
Method and structure for loading data into several IC devices |
June 17, 1997 |
| An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. |
| 5631577 |
Synchronous dual port RAM |
May 20, 1997 |
| A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, |
| 5600271 |
Input signal interface with independently controllable pull-up and pull-down circuitry |
February 4, 1997 |
| An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., |
| 5598424 |
Error detection structure and method for serial or parallel data stream using partial polynomial |
January 28, 1997 |
| The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end reca |
| 5592105 |
Configuration logic to eliminate signal contention during reconfiguration |
January 7, 1997 |
| A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structu |
| 5581199 |
Interconnect architecture for field programmable gate array using variable length conductors |
December 3, 1996 |
| An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output l |
| 5566123 |
Synchronous dual port ram |
October 15, 1996 |
| A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, |
| 5523963 |
Logic structure and circuit for fast carry |
June 4, 1996 |
| Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the ca |
| 5489858 |
Soft wakeup output buffer |
February 6, 1996 |
| Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passive |
| 5430687 |
Programmable logic device including a parallel input device for loading memory cells |
July 4, 1995 |
| A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupl |
| 5410194 |
Asynchronous or synchronous load multifunction flip-flop |
April 25, 1995 |
| According to the present invention hardware is provided in a user configurable logic integrated circuit chip to allow a user to select multiple storage functions such as D, T, JK, to receive multiple input signals and generate a storage input signal using a function such as OR or MUX |
| 5331220 |
Soft wakeup output buffer |
July 19, 1994 |
| Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passive |
| 5321704 |
Error detection structure and method using partial polynomial check |
June 14, 1994 |
| The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end reca |
| 5140193 |
Programmable connector for programmable logic device |
August 18, 1992 |
| A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to t |
| 4106090 |
Monolithic microcomputer central processor |
August 8, 1978 |
| A central processing unit (CPU) is utilized in combination with external memories and input/output devices to form a Microcomputer System. The CPU is a 16-bit fixed word length processor monolithically integrated onto a single semiconductor chip which uses two's complement arithmetic for |
