| Patent Number |
Title Of Patent |
Date Issued |
| 5208833 |
Multi-level symbol synchronizer |
May 4, 1993 |
| A symbol synchronizer for a communication receiver receiving multi-level data signals includes a reference clock generator for generating a reference clock signal having a predetermined time period, a state change detector for detecting state changes occurring within the received mul |
| 5181227 |
Receiver having a signal detector and bit synchronizer |
January 19, 1993 |
| An apparatus and method for processing a signal is capable of determining the presence of absence of a signal having a predetermined baud rate. By initializing counting registers to either first or second values, and receiving the signal, either the presence or absence of the baud rate m |
| 5122778 |
Serial word comparator |
June 16, 1992 |
| An apparatus for determining if a received binary word corresponds to the true or complement version of a stored binary word includes means for serially multiplexing the bits of each binary word to the inputs of an exclusive OR gate. The exclusive-OR gate generates a logical high signal |
| 5077758 |
Signal detector and bit synchronizer |
December 31, 1991 |
| An apparatus and method for processing a signal is capable of determining the presence or absence of a signal having a predetermined baud rate. By initializing counting registers to either first or second values, and receiving the signal, either the presence or absence of the baud rate m |
| 5063533 |
Reconfigurable deinterleaver/interleaver for block oriented data |
November 5, 1991 |
| A reconfigurable deinterleaver for deinterleaving up to N interleaved codewords, each up to M bits in length comprises a memory array, a memory for storing predetermined deinterleaver parameters, a controller, and column and row selector means. The memory array is configured with N bit |
| 5051999 |
Programmable error correcting apparatus within a paging receiver |
September 24, 1991 |
| A paging receiver receiving message information having one of a plurality of (BCH) code word structures has a programmable error correcting apparatus for correcting bit errors within the message information. The programmable error correcting apparatus may be configured in response to |
| 5049875 |
Method and apparatus for out of range detection in response to nondetection of predetermined bau |
September 17, 1991 |
| A baud rate detector determines the baud rates of signals received by a selective call receiver. If the signals have no detectable baud rate or the baud rate of the received signals does not match that of a plurality of known selective call network transmission baud rates, the selective |
| 4912730 |
High speed reception of encoded data utilizing dual phase resynchronizing clock recovery |
March 27, 1990 |
| A mechanism for recovering respective binary states of an input data signal in synchronism with transitions of the input data signal carries out the following sequence of steps. First, the binary state of the input data signal is sampled in accordance with consecutively occurring transit |
