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Inventor:
Elliott; Robert C.
Address:
Houston, TX
No. of patents:
15
Patents:












Patent Number Title Of Patent Date Issued
7644168 SAS expander January 5, 2010
Systems and methodologies associated with providing additional functionality to a conventional SAS expander are described. One exemplary SAS expander embodiment includes logic for selectively performing source identifier checking for frames received at the SAS expander. The logic may
7340551 Bridge permitting access by multiple hosts to a single ported storage drive March 4, 2008
A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the hosts to the single-ported storage drive so that the bridge need not store read or write data
7035952 System having storage subsystems and a link coupling the storage subsystems April 25, 2006
A system includes plural storage subsystems each having a controller and an expander to couple to storage devices. The controller accesses the storage devices through the expander, and the expander has interfaces for coupling to the storage devices. The system further includes an int
7028106 Remapping routing information entries in an expander April 11, 2006
A system includes a peripheral device and an expander having interfaces to couple to one or more peripheral devices and an expander. The expander has a storage to store entries containing routing information used to route a request received by the expander to one of the interfaces, w
6675244 SCSI data rate speed determination January 6, 2004
The method of the present invention enables a SCSI repeater to dynamically determine the speed of an input device and adjust the repeater's output speed accordingly. Thus, the SCSI repeater can transparently connect independent SCSI buses that are connected to different devices with
6546497 SCSI clock stretching April 8, 2003
A SCSI initiator, repeater, or device is provided that stretches an initial assertion of the REQ# or ACK# clock signals on the SCSI bus after a period of inactivity on the SCSI data lines. This discharges built up charge allowing greater signal integrity on ensuing clocks.
6279087 System and method for maintaining coherency and improving performance in a bus bridge supporting August 21, 2001
A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain s
6070215 Computer system with improved transition to low power operation May 30, 2000
A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by
5999198 Graphics address remapping table entry feature flags for customizing the operation of memory pag December 7, 1999
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core lo
5990914 Generating an error signal when accessing an invalid memory page November 23, 1999
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core lo
5936640 Accelerated graphics port memory mapped status and control registers August 10, 1999
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core lo
5933158 Use of a link bit to fetch entries of a graphic address remapping table August 3, 1999
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core lo
5914730 System and method for invalidating and updating individual GART table entries for accelerated gr June 22, 1999
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core lo
5914727 Valid flag for disabling allocation of accelerated graphics port memory space June 22, 1999
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core lo
5838993 System for DMA controller sharing control signals in conventional mode and having separate contr November 17, 1998
A distributed direct memory access (DMA) architecture where DMA controllers are modified to create isolated DMA channels. Each isolated channel includes its own set of uniquely addressable registers which provide functional compatibility with conventional DMA controllers. A DMA master










 
 
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