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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
El-Ayat; Khaled Ahmad
Address:
Cupertino, CA
No. of patents:
2
Patents:












Patent Number Title Of Patent Date Issued
6392437 Programmable multi-standard I/O architecture for FPGAs May 21, 2002
The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be
6242943 Programmable multi-standard I/O architecture for FPGAS June 5, 2001
The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be










 
 
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