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Inventor:
Edirisooriya; Samantha J.
Address:
Tempe, AZ
No. of patents:
29
Patents:












Patent Number Title Of Patent Date Issued
8156406 Method and system for syndrome generation and data recovery April 10, 2012
A method and system for syndrome generation and data recovery is described. The system includes a parity generator coupled to one or more storage devices to generate parity for data recovery. The parity generator includes a first comparator to generate a first parity factor based on
7966477 Power optimized replay of blocked operations in a pipilined architecture June 21, 2011
A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking
7765349 Apparatus and method for arbitrating heterogeneous agents in on-chip busses July 27, 2010
A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent ownership of a bus to eac
7757046 Method and apparatus for optimizing line writes in cache coherent systems July 13, 2010
A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient nu
7725683 Apparatus and method for power optimized replay via selective recirculation of instructions May 25, 2010
A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking
7698476 Implementing bufferless direct memory access (DMA) controllers using split transactions April 13, 2010
According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including a
7685379 Cache memory to support a processor's power mode of operation March 23, 2010
A system, method, and apparatus for a cache memory to support a low power mode of operation.
7640387 Method and apparatus for implementing heterogeneous interconnects December 29, 2009
Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is indepen
7634603 System and apparatus for early fixed latency subtractive decoding December 15, 2009
Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may t
7487299 Cache memory to support a processor's power mode of operation February 3, 2009
A system, method, and apparatus for a cache memory to support a low power mode of operation.
7464227 Method and apparatus for supporting opportunistic sharing in coherent multiprocessors December 9, 2008
A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replace
7447810 Implementing bufferless Direct Memory Access (DMA) controllers using split transactions November 4, 2008
According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including a
7428607 Apparatus and method for arbitrating heterogeneous agents in on-chip busses September 23, 2008
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at leas
7406553 System and apparatus for early fixed latency subtractive decoding July 29, 2008
Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may t
7406552 Systems and methods for early fixed latency subtractive decoding including speculative acknowled July 29, 2008
Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively, or conditionally, acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bu
7404043 Cache memory to support a processor's power mode of operation July 22, 2008
A system, method, and apparatus for a cache memory to support a low power mode of operation.
7360007 System including a segmentable, shared bus April 15, 2008
A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adapted to select sign
7353317 Method and apparatus for implementing heterogeneous interconnects April 1, 2008
Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is indepen
7343546 Method and system for syndrome generation and data recovery March 11, 2008
A method and system for syndrome generation and data recovery is described. The system includes a recovery device coupled to one or more storage devices to recover data in the storage devices. The recovery device includes a first comparator to generate a first parity factor based on
7330998 Data integrity verification February 12, 2008
In one embodiment, a method is provided. The method of this embodiment may include verifying, at least in part, integrity of first check data and a plurality of data blocks. The first check data may be generated based at least in part upon the plurality of data blocks. The verifying may
7290093 Cache memory to support a processor's power mode of operation October 30, 2007
A system, method, and apparatus for a cache memory to support a low power mode of operation.
7234028 Power/performance optimized cache using memory write prevention through write snarfing June 19, 2007
A multiprocessor system may include multiple processors and multiple caches associated with the processors. The system may employ a memory snarfing technique to reduce writes to the system (or main) memory. Cache-ownership capable agents, e.g., agents with write-back caches, may snar
7219176 System and apparatus for early fixed latency subtractive decoding May 15, 2007
A method and apparatus for fixed latency subtractive decoding. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accom
7159077 Direct processor cache access within a system having a coherent multi-processor protocol January 2, 2007
A computer system has a plurality of processors in a multiprocessor system with each processor associated with a cache memory. The cache traffic is monitored by the respective processors to determine the load for each of the cache memories. Signals corresponding to the cache loads are
7143220 Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chi November 28, 2006
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at leas
7100001 Methods and apparatus for cache intervention August 29, 2006
Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., "exclusive" or "shared") are provided. In one embodiment, a first cache holds the memory block in an "exclusive" state prior to the
7062613 Methods and apparatus for cache intervention June 13, 2006
Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds the memory block p
6983348 Methods and apparatus for cache intervention January 3, 2006
Methods and Apparatus for cache-to-cache transfers upon snooping a cache interconnect to detect a memory read request associated with a cache memory block cached in a first cache and a second cache. Upon a cache hit to a first and a second cache, supplying the cached memory block from th
6775748 Methods and apparatus for transferring cache block ownership August 10, 2004
Methods and apparatus for transferring cache block ownership from a first cache to a second cache without performing a writeback to a main memory are disclosed. Prior to the ownership transfer, the first cache holds the memory block in an "owned" state, and the second cache holds the sam










 
 
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