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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Dyer; Thomas W
Address:
Pleasant Valley, NY
No. of patents:
66
Patents:


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Patent Number Title Of Patent Date Issued
8293631 Semiconductor devices having tensile and/or compressive stress and methods of manufacturing October 23, 2012
Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an ep
8198194 Methods of forming p-channel field effect transistors having SiGe source/drain regions June 12, 2012
Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spac
8159031 SOI substrates and SOI devices, and methods for forming the same April 17, 2012
An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator,
8110464 SOI protection for buried plate implant and DT bottle ETCH February 7, 2012
An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench. The initial
8063449 Semiconductor devices and methods of manufacture thereof November 22, 2011
Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least
7989357 Method of patterning semiconductor structure and structure thereof August 2, 2011
Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protec
7968910 Complementary field effect transistors having embedded silicon source and drain regions June 28, 2011
A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitax
7964910 Planar field effect transistor structure having an angled crystallographic etch-defined source/d June 21, 2011
Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a
7943474 EDRAM including metal plates May 17, 2011
A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. An upper electrode is then forme
7923365 Methods of forming field effect transistors having stress-inducing sidewall insulating spacers t April 12, 2011
Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly dop
7911001 Methods for forming self-aligned dual stress liners for CMOS semiconductor devices March 22, 2011
CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
7910451 Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor March 22, 2011
A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by deposition of a
7906384 Semiconductor devices having tensile and/or compressive stress and methods of manufacturing March 15, 2011
A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices to enhance channel strain. The method includes relaxing a gate structure using a low temperature thermal creep process to enhance channel strain. The g
7884448 High performance 3D FET structures, and methods for forming the same using preferential crystall February 8, 2011
The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along
7868461 Embedded interconnects, and methods for forming same January 11, 2011
The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive in
7863693 Forming conductive stud for semiconductive devices January 4, 2011
Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact
7863646 Dual oxide stress liner January 4, 2011
A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is posit
7847357 High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and December 7, 2010
The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-cha
7816231 Device structures including backside contacts, and methods for forming same October 19, 2010
The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located
7808082 Structure and method for dual surface orientations for CMOS transistors October 5, 2010
The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that pre
7790622 Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes September 7, 2010
Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
7772095 Integrated circuit having localized embedded SiGe and method of manufacturing August 10, 2010
An integrated circuit (IC) with localized SiGe embedded in a substrate and a method of manufacturing the IC is provided. The method includes forming recesses in a substrate on each side of a gate structure and remote from a shallow trench isolation structure. The method further includes
7750429 Self-aligned and extended inter-well isolation structure July 6, 2010
A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor
7749903 Gate patterning scheme with self aligned independent gate etch July 6, 2010
A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is
7741188 Deep trench (DT) metal-insulator-metal (MIM) capacitor June 22, 2010
A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subseq
7736966 CMOS devices with hybrid channel orientations and method for fabricating the same June 15, 2010
The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and
7728364 Enhanced mobility CMOS transistors with a V-shaped channel with self-alignment to shallow trench June 1, 2010
The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provide
7718993 Pattern enhancement by crystallographic etching May 18, 2010
A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention.
7667255 Deep trench inter-well isolation structure February 23, 2010
A deep trench is formed in a semiconductor substrate. The deep trench may comprise a pair of parallel substantially vertical sidewalls having a constant separation distance. A set of outer substantially vertical sidewalls may have a closed shape in a horizontal cross-section. At least
7666721 SOI substrates and SOI devices, and methods for forming the same February 23, 2010
An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator,
7652336 Semiconductor devices and methods of manufacture thereof January 26, 2010
Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one
7635899 Structure and method to form improved isolation in a semiconductor device December 22, 2009
A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrat
7598572 Silicided polysilicon spacer for enhanced contact area October 6, 2009
An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the
7598540 High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and October 6, 2009
The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-cha
7582516 CMOS devices with hybrid channel orientations, and methods for fabricating the same using facete September 1, 2009
The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region contains a protrudin
7569489 High performance 3D FET structures, and methods for forming the same using preferential crystall August 4, 2009
The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along
7569446 Semiconductor structure and method of manufacture August 4, 2009
A complimentary metal oxide semiconductor and a method of manufacturing the same using a self-aligning process to form one of the stacks of device. The method includes depositing an oxide layer over a portion of a metal layer over an nFET region of a CMOS structure and etching the metal
7566949 High performance 3D FET structures, and methods for forming the same using preferential crystall July 28, 2009
The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along
7560382 Embedded interconnects, and methods for forming same July 14, 2009
The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive in
7550330 Deep junction SOI MOSFET with enhanced edge body contacts June 23, 2009
A semiconductor structure is provided that has body contacts that are located at the edges of the device channel and a buried insulating region under the device channel that is shallower than the buried insulating regions under the source/drain junctions. A method of forming such a s
7528451 CMOS gate conductor having cross-diffusion barrier May 5, 2009
A gate conductor is provided for a transistor pair including an n-type field effect transistor ("NFET") having an NFET active semiconductor region and a p-type field effect transistor ("PFET") having a PFET active semiconductor region, where the NFET and PFET active semiconductor reg
7517767 Forming conductive stud for semiconductive devices April 14, 2009
Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact
7504309 Pre-silicide spacer removal March 17, 2009
A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not
7504299 Folded node trench capacitor March 17, 2009
A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting the one or more groun
7488660 Extended raised source/drain structure for enhanced contact area and method for forming extended February 10, 2009
A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 .ANG. to about
7488659 Structure and methods for stress concentrating spacer February 10, 2009
A stress-concentrating spacer structure is a stack of an upper gate spacer with a low Young's modulus and a lower gate spacer with a high Young's modulus. The stacked spacer structure surrounds the gate electrode. The stress-concentrating spacer structure may contact an inner gate spacer
7485520 Method of manufacturing a body-contacted finfet February 3, 2009
A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the s
7485516 Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offse February 3, 2009
A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from th
7485508 Two-sided semiconductor-on-insulator structures and methods of manufacturing the same February 3, 2009
Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then
7482215 Self-aligned dual segment liner and method of manufacturing the same January 27, 2009
A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner,
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