| Patent Number |
Title Of Patent |
Date Issued |
| RE38078 |
Graphical rendering system using simultaneous parallel query Z-buffer and method therefor |
April 15, 2003 |
| Apparatus and method for a Parallel Query Z-coordinate Buffer .[.are described. The apparatus and method.]. perform a keep/discard decision on screen coordinate geometry before the geometry is converted or rendered into individual display screen pixels by implementing a parallel searchin |
| 7623135 |
Method and apparatus for display image adjustment |
November 24, 2009 |
| Method and apparatus for display image adjustment is described. More particularly, handles associated with polygon vertices of a polygon rendered image are provided as a graphical user interface (GUI). These handles may be selected and moved by a user with a cursor pointing device to |
| 7526634 |
Counter-based delay of dependent thread group execution |
April 28, 2009 |
| Systems and methods for synchronizing processing work performed by threads, cooperative thread arrays (CTAs), or "sets" of CTAs. A central processing unit can load launch commands for a first set of CTAs and a second set of CTAs in a pushbuffer, and specify a dependency of the second |
| 7167181 |
Deferred shading graphics pipeline processor having advanced features |
January 23, 2007 |
| A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred |
| 7164426 |
Method and apparatus for generating texture |
January 16, 2007 |
| A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at differe |
| 7009605 |
System, method and computer program product for generating a shader program |
March 7, 2006 |
| A method and computer program product are provided for generating a shader program. Initially, a file associated with a graphics effect is a selected. Such file is then read and processed. A shader program is subsequently generated based on the processing of the file to apply the gra |
| 6717576 |
Deferred shading graphics pipeline processor having advanced features |
April 6, 2004 |
| A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred |
| 6693639 |
Graphics processor with pipeline state storage and retrieval |
February 17, 2004 |
| A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to |
| 6671747 |
System, apparatus, method, and computer program for execution-order preserving uncached write co |
December 30, 2003 |
| A mechanism that allows an application program running on a processor, to send data to a device using a medium that temporarily stores data and changes the order of the data dispatch on the way to the device. An inventive Random-In-First-Out (RIFO) buffer or memory device that restores |
| 6664959 |
Method and apparatus for culling in a graphics processor with deferred shading |
December 16, 2003 |
| Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives |
| 6614444 |
Apparatus and method for fragment operations in a 3D-graphics pipeline |
September 2, 2003 |
| Apparatus and methods for rendering 3D graphics images. The apparatus include a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a fragment-operations pipeline, coupled to the port and to the output, the pipeline including a |
| 6597363 |
Graphics processor with deferred shading |
July 22, 2003 |
| Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and |
| 6577317 |
Apparatus and method for geometry operations in a 3D-graphics pipeline |
June 10, 2003 |
| An apparatus and methods for rendering 3D-graphics images preferably includes a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a geometry-operations pipeline, coupled to the port and to the output, the geometry-operations |
| 6577305 |
Apparatus and method for performing setup operations in a 3-D graphics pipeline using unified pr |
June 10, 2003 |
| The present invention provides post tile sorting setup in a tiled graphics pipeline architecture. In particular, the present invention determines a set of clipping points that identify intersections of a primitive with a tile. The mid-pipeline setup unit is adapted to compute a minimum d |
| 6552723 |
System, apparatus and method for spatially sorting image data in a three-dimensional graphics pi |
April 22, 2003 |
| The present invention is a mid-pipeline sorting unit that sorts image data mid-pipeline in a tiled 3-D graphics pipeline architecture. The image data includes vertices of geometric primitives. The mid-pipeline sorting determines whether a geometric primitive intersects a region of a 2-D |
| 6525737 |
Graphics processor with pipeline state storage and retrieval |
February 25, 2003 |
| A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to |
| 6476807 |
Method and apparatus for performing conservative hidden surface removal in a graphics processor |
November 5, 2002 |
| Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives |
| 6288730 |
Method and apparatus for generating texture |
September 11, 2001 |
| A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different |
| 6285378 |
Method and apparatus for span and subspan sorting rendering system |
September 4, 2001 |
| A data shifting capability that permits sorting the data in addition to searching for obtaining real-time performance in color, with high quality imagery through a simple search of a spacial database based on a rectangularly shaped search region or range search. A sorting Magnitude C |
| 6268875 |
Deferred shading graphics pipeline processor |
July 31, 2001 |
| Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor ( |
| 6229553 |
Deferred shading graphics pipeline processor |
May 8, 2001 |
| Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DS |
| 6166554 |
Flexible electrical test fixture for integrated circuits on prototype and production printed cir |
December 26, 2000 |
| An electrical test fixture used to connect the probes of an electronic test instrument to the pins of any integrated circuit. Made from flexible material, the fixture folds above the integrated circuit under test bringing test point pins to useable position. The integrated circuit us |
| 6005403 |
Flexible electrical test fixture for integrated circuits on prototype and production printed cir |
December 21, 1999 |
| An electrical test fixture used to connect the probes of an electronic test instrument to the pins of any integrated circuit. Made from flexible material, the fixture folds above the integrated circuit under test bringing test point pins to useable position. The integrated circuit us |
| 5977987 |
Method and apparatus for span and subspan sorting rendering system |
November 2, 1999 |
| A data shifting capability that permits sorting the data in addition to searching for obtaining real-time performance in color, with high quality imagery through a simple search of a spacial database based on a rectangularly shaped search region or range search. A sorting Magnitude C |
| 5692911 |
Flexible electrical test fixure for integrated circuits on prototype and production printed circ |
December 2, 1997 |
| An electrical test fixture used to connect the probes of an electronic test instrument to the pins of any integrated circuit. Made from flexible material, the fixture folds above the integrated circuit under test bringing test point pins to useable position. The integrated circuit us |
| 5572634 |
Method and apparatus for spatial simulation acceleration |
November 5, 1996 |
| Apparatus and method for detecting unconstrained collisions between three-dimensional moving objects are described. The apparatus and method addresses the problems associated with handling objects with substance passing through each other in three-dimensional space. When objects coll |
| 4996666 |
Content-addressable memory system capable of fully parallel magnitude comparisons |
February 26, 1991 |
| A content-addressable memory for storing a plurality of words, each word comprising a plurality of data subfields, and each data subfield comprising a plurality of data bits. Query operations simultaneously compare input data to all subfields in all words and selectably test each sub |
