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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Dulong; Carole
Address:
Saratoga, CA
No. of patents:
55
Patents:


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Patent Number Title Of Patent Date Issued
8565537 Methods and apparatus for retrieving images from a large collection of images October 22, 2013
A processing system may receive an example image for use in querying a collection of digital images. The processing system may use local and global feature descriptors to perform a content-based image comparison of the digital images with the example image, to automatically rank the
8200027 Methods and apparatus for retrieving images from a large collection of images June 12, 2012
An image retrieval program (IRP) may be used to query a collection of digital images. The IRP may include a mining module to use local and global feature descriptors to automatically rank the digital images in the collection with respect to similarity to a user-selected positive exam
8185571 Processor for performing multiply-add operations on packed data May 22, 2012
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations
7840076 Methods and apparatus for retrieving images from a large collection of images November 23, 2010
An image retrieval program (IRP) may be used to query a collection of digital images. The IRP may include a mining module to use local and global feature descriptors to automatically rank the digital images in the collection with respect to similarity to a user-selected positive exam
7739662 Methods and apparatus to analyze processor systems June 15, 2010
Methods and apparatus are disclosed to analyze processor system. An example method to analyze execution of a multi-threaded program on a processor system includes generating a first program trace associated with the execution of a first thread, generating a first list of execution fr
7509367 Method and apparatus for performing multiply-add operations on packed data March 24, 2009
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations
7424505 Method and apparatus for performing multiply-add operations on packed data September 9, 2008
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations
7395298 Method and apparatus for performing multiply-add operations on packed data July 1, 2008
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations
7373490 Emptying packed data state during execution of packed data instructions May 13, 2008
A method in a computer system, one embodiment includes accessing a packed data instruction and generating a corresponding set of control bits to cause a processor to alter a top of stack to zero of a programmer visible register file, accessing a floating point instruction and generating
7149882 Processor with instructions that operate on different data types stored in the same single logic December 12, 2006
A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number
7093102 Code sequence for vector gather and scatter August 15, 2006
Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required complex address calculation hardware and other hardware to perform vector gather and scatter
6823353 Method and apparatus for multiplying and accumulating complex numbers in a digital filter November 23, 2004
The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coef
6792523 Processor with instructions that operate on different data types stored in the same single logic September 14, 2004
A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first instruction type operates on the contents of what at least logically appears to software as a single
6751725 Methods and apparatuses to clear state for operation of a stack June 15, 2004
Methods and apparatuses to clear state for operation of a stack. According to one embodiment of the invention, a processor comprises a set of one or more storage areas and a decode unit. The set of one or more storage areas are to store a plurality of tags and a top of stack indication,
6502117 Data manipulation instruction for enhancing value and efficiency of complex arithmetic December 31, 2002
A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first storage area to higher order bits o
6484255 Selective writing of data elements from packed data based upon a mask using predication November 19, 2002
A method and apparatus for selectively writing data elements from packed data based upon a mask using predication. In one embodiment of the invention, for each data element of a packed data operand, the following is performed in parallel processing units: determining a predicate value
6470370 Method and apparatus for multiplying and accumulating complex numbers in a digital filter October 22, 2002
The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coef
6385634 Method for performing multiply-add operations on packed data May 7, 2002
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on
6272512 Data manipulation instruction for enhancing value and efficiency of complex arithmetic August 7, 2001
A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first storage area to higher order bits o
6266686 Emptying packed data state during execution of packed data instructions July 24, 2001
A method in a computer system which includes receiving a first instruction which indicates indicates termination of execution of instructions which operate upon packed data stored in a first storage area. The first storage area is used for modifying data responsive to execution of floati
6237016 Method and apparatus for multiplying and accumulating data samples and complex coefficients May 22, 2001
A method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the
6212627 System for converting packed integer data into packed floating point data in reduced time April 3, 2001
A method and apparatus for converting a packed integer data item having first and second data elements, to a packed floating-point data item. In one embodiment, a method includes moving the first data element of the integer data item to a first data element of a first intermediate data
6170997 Method for executing instructions that operate on different data types stored in the same single January 9, 2001
A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software convention
6163764 Emulation of an instruction set on an instruction set architecture transition December 19, 2000
A method and apparatus for emulating an instruction on a processor. The instruction operates on an operand in a first data format and the processor operates in a second data format. The operand is converted from the first data format to the second data format. The processor then exec
6128614 Method of sorting numbers to obtain maxima/minima values with ordering October 3, 2000
A technique for sorting packed numbers of two operands into minima or maxima operand with their indices to identify the origin of those selected values. After packing two source operands with a plurality of data elements containing numerical values, greater-than comparison operation is
6058408 Method and apparatus for multiplying and accumulating complex numbers in a digital filter May 2, 2000
The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coef
6036350 Method of sorting signed numbers and solving absolute differences using packed instructions March 14, 2000
A technique for sorting packed signed numbers of two operands into maxima and minima operands and solving absolute differences for each pair of corresponding values of maxima and minima. After packing two source operands with a plurality of data elements containing signed values, a g
6035316 Apparatus for performing multiply-add operations on packed data March 7, 2000
A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first
6018351 Computer system performing a two-dimensional rotation of packed data representing multimedia inf January 25, 2000
A computer system for processing multimedia data, wherein the data is transformed from a first domain to a second domain by performing two dimensional rotation on the data. The computer system includes a memory having stored therein a set of packed data sequences having data elements
5984515 Computer implemented method for providing a two dimensional rotation of packed data November 16, 1999
In a computer system having stored therein a first and a second packed data having corresponding data elements, a method for generating a two dimensional rotation of said packed data. The method includes the steps of generating a first set of intermediate results in response to a first
5983257 System for signal processing using multiply-add operations November 9, 1999
A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine fo
5983256 Apparatus for performing multiply-add operations on packed data November 9, 1999
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on
5983253 Computer system for performing complex digital filters November 9, 1999
A method and apparatus for performing complex digital filters. According to one aspect of the invention, a computer system generally having a transmitting unit, a processor, and a storage device is described. The storage device is coupled to the processor and has stored therein a rou
5940859 Emptying packed data state during execution of packed data instructions August 17, 1999
A method in a computer system which includes receiving a first instruction which indicates indicates termination of execution of instructions which operate upon packed data stored in a first storage area. The first storage area is used for modifying data responsive to execution of floati
5936872 Method and apparatus for storing complex numbers to allow for efficient complex multiplication o August 10, 1999
The invention provides a method and apparatus for storing complex data in formats which allow efficient complex multiplication operations to be performed and for performing such complex multiplication operations. According to one aspect of the invention, a method for multiplying complex
5935240 Computer implemented method for transferring packed data between register files and memory August 10, 1999
A method for transferring packed data including the steps of first receiving an instruction from a set of instructions for transferring packed data between an extended register file and either an integer register file or a memory. In one embodiment, the extended register file include
5907842 Method of sorting numbers to obtain maxima/minima values with ordering May 25, 1999
A technique for sorting packed numbers of two operands into minima or maxima operand with their indices to identify the origin of those selected values. After packing two source operands with a plurality of data elements containing numerical values, greater-than comparison operation is
5881312 Memory transfer apparatus and method useful within a pattern recognition system March 9, 1999
A computer implemented apparatus and method for transferring information from one set or sets of memory locations to another set or sets of memory locations. The present invention has particular advantageous use within a computer system specially implemented for pattern recognition a
5859997 Method for performing multiply-substrate operations on packed data January 12, 1999
A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operation
5857096 Microarchitecture for implementing an instruction to clear the tags of a stack reference registe January 5, 1999
An apparatus (e.g. a microarchitecture of a microprocessor) comprising a plurality of tags associated with a first storage area indicating that locations in the first storage area are either empty or non-empty responsive to execution of floating point instructions which modify data c
5852726 Method and apparatus for executing two types of instructions that specify registers of a shared December 22, 1998
A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit i
5835748 Method for executing different sets of instructions that cause a processor to perform different November 10, 1998
A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a
5835392 Method for performing complex fast fourier transforms (FFT's) November 10, 1998
A method in a computer system of performing a butterfly stage of a complex fast fourier transform of two input signals. First, a packed multiply add is performed on a first packed complex value generated from a first input signal and a set of trigonometric values to generate a first prod
5825921 Memory transfer apparatus and method useful within a pattern recognition system October 20, 1998
A computer implemented apparatus and method for transferring information from one set or sets of memory locations to another set or sets of memory locations. The present invention has particular advantageous use within a computer system specially implemented for pattern recognition a
5822232 Method for performing box filter October 13, 1998
A computer implemented method for box filtering an array of data. The method includes a first step of filtering the rows of an array. The rows are in packed data sequences, each sequence having a plurality of packed data elements. Each row is filtered by generating copies of the row,
5793661 Method and apparatus for performing multiply and accumulate operations on packed data August 11, 1998
A method of multiplying and accumulating two sets of values in a computer system. A packed multiply add is performed on a first portion of a first set of values packed into a first source and a first portion of a second set of values packed into a second source to generate a first result
5757432 Manipulating video and audio signals using a processor which supports SIMD instructions May 26, 1998
A computer system which manipulates audio and video signals. A multimedia input device which generates an audio and/or video signal is coupled to a processor. The processor is also coupled to a storage device upon which a decompression routine is stored, the decompression routine includi
5752001 Method and apparatus employing Viterbi scoring using SIMD instructions for data recognition May 12, 1998
A computer system includes a single instruction multiple data (SIMD) instruction set. At a first observation time, a first SIMD instruction is used to determine a first plurality of probabilities for the stochastic model to be in a certain set of states after transitioning via a first se
5737561 Method and apparatus for executing an instruction with multiple brancing options in one cycle April 7, 1998
A multi-alternative structure, such as a case instruction, in a computer system that can be executed in one cycle. The computer system of the present invention executes multiple instructions, wherein condition indicators are set according to the execution of each instruction. The mul
5721892 Method and apparatus for performing multiply-subtract operations on packed data February 24, 1998
A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operation
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