| Patent Number |
Title Of Patent |
Date Issued |
| 6420730 |
Elevated transistor fabrication technique |
July 16, 2002 |
| A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed |
| 6104069 |
Semiconductor device having an elevated active region formed in an oxide trench |
August 15, 2000 |
| A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer |
| 6104064 |
Asymmetrical transistor structure |
August 15, 2000 |
| Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produce |
| 6091118 |
Semiconductor device having reduced overlap capacitance and method of manufacture thereof |
July 18, 2000 |
| A semiconductor device and process for manufacture thereof is disclosed in which a gate electrode with reduced overlap capacitance is formed by forming a gate electrode on a surface of a semiconductor and doping edge portions of the gate electrode with a first doping which effectively |
| 6075258 |
Elevated transistor fabrication technique |
June 13, 2000 |
| A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed |
| 6030875 |
Method for making semiconductor device having nitrogen-rich active region-channel interface |
February 29, 2000 |
| A semiconductor device having a nitrogen-rich active region-channel interface and process for fabrication thereof is provided. The nitrogen-rich interface can, for example, can reduce the electric field potential in this region and reduce hot carrier injection effects. Consistent wit |
| 6027978 |
Method of making an IGFET with a non-uniform lateral doping profile in the channel region |
February 22, 2000 |
| A method of making an IGFET with a selectively doped channel region is disclosed. The method includes providing a semiconductor substrate with a device region, forming a gate over the device region, forming a masking layer that partially covers the gate and the device region, implanting |
| 6027964 |
Method of making an IGFET with a selectively doped gate in combination with a protected resistor |
February 22, 2000 |
| A method of making an IGFET with a selectively doped gate in combination with a protected resistor includes the steps of providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor reg |
| 6008096 |
Ultra short transistor fabrication method |
December 28, 1999 |
| A semiconductor process in which the transistor channel is defined by opposing sidewalls of a pair of masking structures formed on an upper surface of a semiconductor substrate. The spacing between the opposed sidewalls is defined by the thickness of the spacer structure formed betwe |
| 6004849 |
Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide c |
December 21, 1999 |
| A method of making an asymmetrical IGFET is disclosed. The method includes providing a semiconductor substrate with an active region, wherein the active region includes a source region and a drain region, forming a gate insulator on the active region, forming a gate on the gate insulator |
| 5970349 |
Semiconductor device having one or more asymmetric background dopant regions and method of manuf |
October 19, 1999 |
| Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a patterned mask with wider openings than conventional masks while substantially maintaining device |
| 5963809 |
Asymmetrical MOSFET with gate pattern after source/drain formation |
October 5, 1999 |
| A process for fabricating a transistor in which a first impurity distribution is introduced into a semiconductor substrate prior to the formation of a conductive gate structure on the semiconductor substrate. The substrate includes a channel region disposed between a source region an |
| 5949092 |
Ultra-high-density pass gate using dual stacked transistors having a gate structure with planari |
September 7, 1999 |
| A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but |
| 5940707 |
Vertically integrated advanced transistor formation |
August 17, 1999 |
| A field-effect transistor and method for making same in which a first source/drain impurity distribution is located at a first depth below an upper surface of the semiconductor substrate and a second source/drain impurity distribution is located at a second depth below the upper surf |
| 5898189 |
Integrated circuit including an oxide-isolated localized substrate and a standard silicon substr |
April 27, 1999 |
| A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but |
| 5888853 |
Integrated circuit including a graded grain structure for enhanced transistor formation and fabr |
March 30, 1999 |
| An elevated transistor formation includes a plurality of planes upon which transistors are formed. The plurality of transistor planes are formed at multiple relative elevations overlying a substrate wafer using deposited polysilicon to form a substrate between the layers. The polysilicon |
| 5885761 |
Semiconductor device having an elevated active region formed from a thick polysilicon layer and |
March 23, 1999 |
| A semiconductor device and process for manufacture thereof is disclosed in which an elevated, active polysilicon region is formed by forming a gate electrode/nitride layer structure on a surface of a semiconductor substrate with spacers formed on adjacent walls to define an active region |
| 5872038 |
Semiconductor device having an elevated active region formed in an oxide trench and method of ma |
February 16, 1999 |
| A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer |
| 5834350 |
Elevated transistor fabrication technique |
November 10, 1998 |
| A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed |
| 5804496 |
Semiconductor device having reduced overlap capacitance and method of manufacture thereof |
September 8, 1998 |
| A semiconductor device and process for manufacture thereof is disclosed in which a gate electrode with reduced overlap capacitance is formed by forming a gate electrode on a surface of a semiconductor and doping edge portions of the gate electrode with a first doping which effectively |
| 5693547 |
Method of making vertical MOSFET with sub-trench source contact |
December 2, 1997 |
| An integrated circuit transistor vertically oriented along a side wall of a shallow trench formed in a semiconductor substrate. The transistor includes a semiconductor substrate, preferably comprised of silicon, into which a shallow transistor trench has been formed. A trench floor of th |
