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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Donze; Richard Lee
Address:
Rochester, MN
No. of patents:
11
Patents:












Patent Number Title Of Patent Date Issued
7935629 Semiconductor scheme for reduced circuit area in a simplified process May 3, 2011
An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created
7696565 FinFET body contact structure April 13, 2010
A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin p
7659733 Electrical open/short contact alignment structure for active region vs. gate region February 9, 2010
An apparatus for measuring a structural characteristic between a polysilicon shape and a silicon area. The apparatus for measuring a structural characteristic between a polysilicon shape and a silicon area comprises the silicon area, and a plurality of polysilicon shapes each having
7626220 Semiconductor scheme for reduced circuit area in a simplified process December 1, 2009
An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created
7453272 Electrical open/short contact alignment structure for active region vs. gate region November 18, 2008
A method is disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the
7336086 Measurement of bias of a silicon area using bridging vertices on polysilicon shapes to create an February 26, 2008
An apparatus and method are disclosed for measuring bias of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon
7317605 Method and apparatus for improving performance margin in logic paths January 8, 2008
An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present
7317217 Semiconductor scheme for reduced circuit area in a simplified process January 8, 2008
An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created
7241649 FinFET body contact structure July 10, 2007
A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin p
7227183 Polysilicon conductor width measurement for 3-dimensional FETs June 5, 2007
An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon "fins". A first resisto
7183780 Electrical open/short contact alignment structure for active region vs. gate region February 27, 2007
An apparatus for measuring alignment of polysilicon shapes to a silicon area. Each polysilicon shape in a first plurality of polysilicon shapes has a bridging vertex positioned near the silicon area. Each polysilicon shape in a second plurality of polysilicon shapes has a bridging vertex










 
 
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