| Patent Number |
Title Of Patent |
Date Issued |
| 7302616 |
Method and apparatus for performing bus tracing with scalable bandwidth in a data processing sys |
November 27, 2007 |
| An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing un |
| 7284097 |
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively |
October 16, 2007 |
| A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol |
| 7213169 |
Method and apparatus for performing imprecise bus tracing in a data processing system having a d |
May 1, 2007 |
| An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and |
| 7058767 |
Adaptive memory access speculation |
June 6, 2006 |
| A method and system for speculatively pre-fetching data from a memory. A memory controller on a data bus "snoops" data requests put on the data bus by a bus control logic. Based on information in the header of the data request, such as transaction type, tag, transaction size, etc., a |
| 7017024 |
Data processing system having no system memory |
March 21, 2006 |
| A data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the |
| 6970976 |
Layered local cache with lower level cache optimizing allocation mechanism |
November 29, 2005 |
| A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning t |
| 6963967 |
System and method for enabling weak consistent storage advantage to a firmly consistent storage |
November 8, 2005 |
| Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier opera |
| 6920521 |
Method and system of managing virtualized physical memory in a data processing system |
July 19, 2005 |
| A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the |
| 6907494 |
Method and system of managing virtualized physical memory in a memory controller and processor s |
June 14, 2005 |
| A processor contains a move engine and a memory controller contains a mapping engine that, together, transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores current and new real addresses that enab |
| 6904490 |
Method and system of managing virtualized physical memory in a multi-processor system |
June 7, 2005 |
| A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical |
| 6901485 |
Memory directory management in a multi-node computer system |
May 31, 2005 |
| A computer system includes a home node and one or more remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, a home system memory, a memory directory including a pl |
| 6886079 |
Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform me |
April 26, 2005 |
| A non-uniform memory access (NUMA) computer system includes at least one remote node and a home node coupled by a node interconnect. The home node contains a home system memory and a memory controller. In response to receipt of a data request from a remote node, the memory controller |
| 6880073 |
Speculative execution of instructions and processes before completion of preceding barrier opera |
April 12, 2005 |
| Described is a data processing system and processor that provides full multiprocessor speculation by which all instructions subsequent to barrier operations in a instruction sequence are speculatively executed before the barrier operation completes on the system bus. The processor compri |
| 6801984 |
Imprecise snooping based invalidation mechanism |
October 5, 2004 |
| A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided a set of directional bits in addition to the coherency state bits and the address tag. The |
| 6763434 |
Data processing system and method for resolving a conflict between requests to modify a shared c |
July 13, 2004 |
| Disclosed herein are a data processing system and method of operating a data processing system that arbitrate between conflicting requests to modify data cached in a shared state and that protect ownership of the cache line granted during such arbitration until modification of the data |
| 6763433 |
High performance cache intervention mechanism for symmetric multiprocessor systems |
July 13, 2004 |
| Upon snooping an operation in which an intervention is permitted or required, an intervening cache may elect to source only that portion of a requested cache line which is actually required, rather than the entire cache line. For example, if the intervening cache determines that the |
| 6760817 |
Method and system for prefetching utilizing memory initiated prefetch write operations |
July 6, 2004 |
| A computer system includes a processing unit, a system memory, and a memory controller coupled to the processing unit and the system memory. According to the present invention, the memory controller accesses the system memory to obtain prefetch data and transmits the prefetch data to the |
| 6760809 |
Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated |
July 6, 2004 |
| A non-uniform memory access (NUMA) computer system and associated method of operation are disclosed. The NUMA computer system includes at least a remote node and a home node coupled to an interconnect. The remote node contains at least one processing unit coupled to a remote system memor |
| 6754782 |
Decentralized global coherency management in a multi-node computer system |
June 22, 2004 |
| A non-uniform memory access (NUMA) computer system includes a first node and a second node coupled by a node interconnect. The second node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, and a controller coupled to the |
| 6748518 |
Multi-level multiprocessor speculation mechanism |
June 8, 2004 |
| Disclosed is a processor, which reduces issuing of unnecessary barrier operations during instruction processing. The processor comprises an instruction sequencing unit and a load store unit (LSU) that issues a group of memory access requests that precede a barrier instruction in an i |
| 6728873 |
System and method for providing multiprocessor speculation within a speculative branch path |
April 27, 2004 |
| Disclosed is a method of operation within a processor, that enhances speculative branch processing. A speculative execution path contains an instruction sequence that includes a barrier instruction followed by a load instruction. While a barrier operation associated with the barrier |
| 6725340 |
Mechanism for folding storage barrier operations in a multiprocessor system |
April 20, 2004 |
| Disclosed is a processor that reduces barrier operations during instruction processing. An instruction sequence includes a first barrier instruction and a second barrier instruction with a store instruction in between the first and second barrier instructions. A store request associated |
| 6721856 |
Enhanced cache management mechanism via an intelligent system bus monitor |
April 13, 2004 |
| In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access, snoop operation, and system controller hint information for the corresponding cache line. Each entry includes different subentries for different proc |
| 6711652 |
Non-uniform memory access (NUMA) data processing system that provides precise notification of re |
March 23, 2004 |
| A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node including a home system memory. The remote node includes a plurality of snoopers coupled to a local interconnect. The plurality of snoopers includes a cache that caches |
| 6704843 |
Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange |
March 9, 2004 |
| System bus snoopers within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the dynamic application sequence behavior information for the target cache line to their snoop responses. The system controller, |
| 6701416 |
Cache coherency protocol with tagged intervention of modified values |
March 2, 2004 |
| A cache coherency protocol uses a "Tagged" coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migra |
| 6691220 |
Multiprocessor speculation mechanism via a barrier speculation flag |
February 10, 2004 |
| A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and while the barrier operation is pending, a load request associated with the load instructio |
| 6662275 |
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer |
December 9, 2003 |
| A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. |
| 6662216 |
Fixed bus tags for SMP buses |
December 9, 2003 |
| According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respe |
| 6658538 |
Non-uniform memory access (NUMA) data processing system having a page table including node-speci |
December 2, 2003 |
| A non-uniform memory access (NUMA) data processing system includes a plurality of nodes coupled to a node interconnect. The plurality of nodes contain a plurality of processing units and at least one system memory having a table (e.g., a page table) resident therein. The table includes |
| 6658536 |
Cache-coherency protocol with recently read state for extending cache horizontally |
December 2, 2003 |
| A method of extending a cache of a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. A value is loaded from system memory into one or |
| 6654857 |
Non-uniform memory access (NUMA) computer system having distributed global coherency management |
November 25, 2003 |
| A computer system includes a home node and one or more remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, a home system memory, and a memory controller coupled to th |
| 6633959 |
Non-uniform memory access (NUMA) data processing system that provides notification of remote dea |
October 14, 2003 |
| A non-uniform memory access (NUMA) computer system includes a node interconnect to which a remote node and a home node are coupled. The home node contains a home system memory, and the remote node includes at least one processing unit and a cache. In response to the cache deallocating an |
| 6631450 |
Symmetric multiprocessor address bus protocol with intra-cache line access information |
October 7, 2003 |
| System bus masters within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the historical access information for the target cache line to their requests. Snoopers and/or the system controller, which may a |
| 6629214 |
Extended cache coherency protocol with a persistent "lock acquired" state |
September 30, 2003 |
| A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache state |
| 6629212 |
High speed lock acquisition mechanism with time parameterized cache coherency states |
September 30, 2003 |
| A multiprocessor data processing system requires careful management to maintain cache coherency. In conventional systems using a MESI approach, two or more processors will often compete for ownership of a common cache line. As a result, ownership of the cache line will frequently "bounce |
| 6629210 |
Intelligent cache management mechanism via processor access sequence analysis |
September 30, 2003 |
| In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access information for the corresponding cache line. The historical processor access information includes different subentries for each different processor which |
| 6629209 |
Cache coherency protocol permitting sharing of a locked data granule |
September 30, 2003 |
| A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache state |
| 6625701 |
Extended cache coherency protocol with a modified store instruction lock release indicator |
September 23, 2003 |
| A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache state |
| 6625660 |
Multiprocessor speculation mechanism for efficiently managing multiple barrier operations |
September 23, 2003 |
| Disclosed is a method of operation within a processor that permits load instructions to be issued speculatively. An instruction sequence is received that includes multiple barrier instructions and a load instruction that follows the barrier instructions in the instruction sequence. I |
| 6615322 |
Two-stage request protocol for accessing remote memory data in a NUMA data processing system |
September 2, 2003 |
| A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node having a home system memory. The remote node includes a local interconnect, a processing unit and at least one cache coupled to the local interconnect, and a node contr |
| 6615321 |
Mechanism for collapsing store misses in an SMP computer system |
September 2, 2003 |
| A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value for a store instruction is the same as a current value already contained in the memory hierarchy, and discarding the store instr |
| 6615320 |
Store collapsing mechanism for SMP computer system |
September 2, 2003 |
| A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value for a store instruction is the same as a current value already contained in the memory hierarchy, and discarding the store instr |
| 6609192 |
System and method for asynchronously overlapping storage barrier operations with old and new sto |
August 19, 2003 |
| Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality of processors coupled to an interconnect. At least one of the processors includes an instru |
| 6606702 |
Multiprocessor speculation mechanism with imprecise recycling of storage operations |
August 12, 2003 |
| Disclosed is a method of operating a processor, by which a speculatively issued load request, which fetches incorrect data, is recycled. An instruction sequence, which includes a barrier instruction and a load instruction that follows the barrier instruction in program order, is rece |
| 6601144 |
Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analy |
July 29, 2003 |
| In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access and snoop operation information for the corresponding cache line. The historical processor access and snoop operation information includes different s |
| 6587926 |
Incremental tag build for hierarchical memory architecture |
July 1, 2003 |
| A method and system for managing a data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device to multiple data storage devices within the hierarchical data storage |
| 6587925 |
Elimination of vertical bus queueing within a hierarchical memory architecture |
July 1, 2003 |
| A method and system for processing a split data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device onto an address bus that is shared by a plurality of data storage |
| 6587924 |
Scarfing within a hierarchical memory architecture |
July 1, 2003 |
| A method and system for scarfing data during a data access transaction within a hierarchical data storage system. A data access request is delivered from a source device to a plurality of data storage devices. The access request includes a target address and a source path tag, wherein |
| 6581139 |
Set-associative cache memory having asymmetric latency among sets |
June 17, 2003 |
| A set-associative cache memory having asymmetric latency among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. The cache memory further includes a means for acce |
