Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Doan; Trung T.
Address:
Boise, ID
No. of patents:
187
Patents:


1 2 3 4










Patent Number Title Of Patent Date Issued
RE39126 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs June 13, 2006
A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is more even with the insulation layer surface than conventional plug formation techniques. Conventional processes result in
RE37104 Planarization of a gate electrode for improved gate patterning over non-planar active area isola March 20, 2001
The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon
RE34583 Method of forming a configuration of interconnections on a semiconductor device having a high in April 12, 1994
A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of in
8124491 Container capacitor structure and method of formation thereof February 28, 2012
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess between proximal pairs of container
7964436 Co-sputter deposition of metal-doped chalcogenides June 21, 2011
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge.sub.xSe.sub.1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with th
7935950 Controllable ovonic phase-change semiconductor memory device and methods of programming the same May 3, 2011
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material o
7871934 Method for an integrated circuit contact January 18, 2011
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The proce
7625795 Container capacitor structure and method of formation thereof December 1, 2009
Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode ("bottom electrodes") of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is ava
7579235 Container capacitor structure and method of formation thereof August 25, 2009
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess between proximal pairs of container
7569485 Method for an integrated circuit contact August 4, 2009
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The proce
7485961 Approach to avoid buckling in BPSG by using an intermediate barrier layer February 3, 2009
A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed
7470344 Chemical dispensing system for semiconductor wafer processing December 30, 2008
A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively onto the wafer and applying a suction to the area immediately surrounding the location at which the chemical is dispensed o
7446393 Co-sputter deposition of metal-doped chalcogenides November 4, 2008
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge.sub.xSe.sub.1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with th
7315082 Semiconductor device having integrated circuit contact January 1, 2008
A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect
7282447 Method for an integrated circuit contact October 16, 2007
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The proce
7282440 Integrated circuit contact October 16, 2007
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect troug
7276448 Method for an integrated circuit contact October 2, 2007
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The proce
7253430 Controllable ovonic phase-change semiconductor memory device August 7, 2007
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An
7247944 Connector assembly July 24, 2007
An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame ov
7224065 Contact/via force fill techniques and resulting structures May 29, 2007
An improved method of forming a semiconductor device structure is disclosed, comprising insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying
7220670 Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and May 22, 2007
A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.
7202104 Co-sputter deposition of metal-doped chalcogenides April 10, 2007
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge.sub.xSe.sub.1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with th
7160785 Container capacitor structure and method of formation thereof January 9, 2007
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess between proximal pairs of container
7153410 Methods and apparatus for electrochemical-mechanical processing of microelectronic workpieces December 26, 2006
Methods and apparatuses for electrochemical-mechanical processing of microelectronic workpieces. One embodiment of an electrochemical processing apparatus in accordance with the invention comprises a workpiece holder configured to receive a microelectronic workpiece, a workpiece elec
7009298 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium March 7, 2006
A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor.
7001481 Method and system providing high flux of point of use activated reactive species for semiconduct February 21, 2006
A method and system providing a high flux of point of use activated reactive species for semiconductor processing wherein a workpiece is exposed to a gaseous atmosphere containing a transmission gas that is substantially nonattenuating to preselected wavelengths of electromagnetic ra
6953743 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium October 11, 2005
A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact
6949464 Contact/via force fill techniques September 27, 2005
An improved semiconductor device fabrication method comprises insertion of a semiconductor wafer into a high-pressure heated chamber and deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The waf
6903010 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium June 7, 2005
A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact
6897467 Controllable ovanic phase-change semiconductor memory device May 24, 2005
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same, are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. A
6890790 Co-sputter deposition of metal-doped chalcogenides May 10, 2005
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge.sub.x Se.sub.1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with t
6885051 Minimally spaced MRAM structures April 26, 2005
A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum cri
6882033 High density direct connect LOC assembly April 19, 2005
An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over
6881974 Probe card for testing microelectronic components April 19, 2005
Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe card may be manufactured by forming a plurality of blind holes in a substrate, with each h
6881667 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium April 19, 2005
A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact
6861351 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium March 1, 2005
A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact
6847535 Removable programmable conductor memory card and associated read/write device and method of oper January 25, 2005
A removable memory card and an associated read/write device and its method of operation are disclosed. The memory card may be formed of a sheet of chalcogenide glass material which has memory storage locations therein defined by the locations of conductive read/write elements of the
6846739 MOCVD process using ozone as a reactant to deposit a metal oxide barrier layer January 25, 2005
An inventive process is disclosed for creating a barrier layer on a silicon substrate of an in-process integrated circuit. The process uses MOCVD to form a metal oxide film. The source gas is preferably an organometallic compound. Ozone is used as an oxidizing agent in order to react wit
6831324 Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and December 14, 2004
A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.
6828812 Test apparatus for testing semiconductor dice including substrate with penetration limiting cont December 7, 2004
A die contacting substrate establishes ohmic contact with the die by means of raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondp
6825107 Method for fabricating a memory chip November 30, 2004
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulativ
6793764 Chemical dispensing system for semiconductor wafer processing September 21, 2004
A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively onto the wafer and applying a suction to the area immediately surrounding the location at which the chemical is dispensed onto
6793736 Method of providing high flux of point of use activated reactive species for semiconductor proce September 21, 2004
A method for providing a high flux of point of use activated reactive species for semiconductor processing wherein a workpiece is exposed to a gaseous atmosphere containing a transmission gas that is substantially nonattenuating to preselected wavelengths of electromagnetic radiation. A
6781145 Controlable ovonic phase-change semiconductor memory device August 24, 2004
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An
6773938 Probe card, e.g., for testing microelectronic components, and methods for making same August 10, 2004
Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe card may be manufactured by forming a plurality of blind holes in a substrate, with each h
6765250 Self-aligned, trenchless mangetoresitive random-access memory (MRAM) structure with sidewall con July 20, 2004
This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the
6753565 Container capacitor array having a common top capacitor plate June 22, 2004
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess between proximal pairs of container cap
6750069 Minimally spaced MRAM structures June 15, 2004
A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum cri
6746934 Atomic layer doping apparatus and method June 8, 2004
An improved atomic layer doping apparatus is disclosed as having multiple doping regions in which individual monolayer species are first deposited and then dopant atoms contained therein are diffused into the substrate. Each doping region is chemically separated from adjacent doping regi
6743724 Planarization process for semiconductor substrates June 1, 2004
A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a
1 2 3 4










 
 
  Recently Added Patents
RF/optical shared aperture for high availability wideband communication RF/FSO links
Wafer processing method and system using multi-zone chuck
Method and apparatus for disease diagnosis and screening using extremely low frequency electromagnetic fields
System and method for wireless messaging in a wireless communication system
Method for transmitting a signal from a transmitter to a receiver in a power line communication network, transmitter, receiver, power line communication modem and power line communication syst
Fibrous laminate interface for security coatings
Software management system for network data processing systems
  Randomly Featured Patents
Liquid droplet discharge head, manufacturing method thereof, and image forming apparatus
Compass
Utilization of a rail pressure predictor model in controlling a common rail fuel injection system
Bearing housing assembly
Nozzle mounted lamp
Interference type low voltage optical light modulator
Fluorescence detection with increased dynamic range
Process for the preparation of 2,3-pyridinedicarboximides
Antisense inhibition of cellular inhibitor of apoptosis-1 expression
Database processing method and system