Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ding; Jian
Address:
San Jose, CA
No. of patents:
22
Patents:












Patent Number Title Of Patent Date Issued
8202441 Process for etching a metal layer suitable for use in photomask fabrication June 19, 2012
Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a metal layer disposed on an optically transparent materi
7737040 Method of reducing critical dimension bias during fabrication of a semiconductor device June 15, 2010
An anti-reflective hard mask layer left on a radiation-blocking layer during fabrication of a reticle provides functionality when the reticle is used in a semiconductor device manufacturing process.
7682518 Process for etching a metal layer suitable for use in photomask fabrication March 23, 2010
Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a metal layer disposed on an optically transparent materi
7521000 Process for etching photomasks April 21, 2009
Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a metal layer disposed on an optically transparent materi
7365014 Reticle fabrication using a removable hard mask April 29, 2008
We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs du
7250309 Integrated phase angle and optical critical dimension measurement metrology for feed forward and July 31, 2007
Methods and apparatus for controlling the critical dimensions and monitoring the phase shift angles of photomasks. Critical dimensions measurement data before wafer processing and after wafer processing are collected by an integrated metrology tool to adjust the process recipe, to de
6818140 Low ceiling temperature process for a plasma reactor with heated source of a polymer-hardening p November 16, 2004
A high plasma density etch process for etching an oxygen-containing layer overlying a non-oxygen containing layer on a workpiece in a plasma reactor chamber, by providing a chamber ceiling overlying the workpiece and containing a semiconductor material, supplying into the chamber a proce
6399511 Plasma etch process in a single inter-level dielectric etch June 4, 2002
A dielectric etch process applicable etching a dielectric layer with an underlying stop layer. It is particularly though not necessarily applicable to forming a dual-damascene interconnect structure by a counterbore process, in which a deep via is etched prior to the formation of a t
6380096 In-situ integrated oxide etch process particularly useful for copper dual damascene April 30, 2002
An integrated in situ oxide etch process particularly useful for a counterbore dual-damascene structure over copper having in one inter-layer dielectric level a lower nitride stop layer, a lower oxide dielectric, a lower nitride stop layer, an upper oxide dielectric layer, and an ant
6361705 Plasma process for selectively etching oxide using fluoropropane or fluoropropylene March 26, 2002
A plasma etch process, particularly applicable to an self-aligned contact etch in a high-density plasma for selectively etching oxide over nitride, although selectivity to silicon is also achieved. In the process, a fluoropropane or a fluoropropylene is a principal etching gas in the
6329292 Integrated self aligned contact etch December 11, 2001
An integrated self aligned contact process includes oxide etch with high oxide etch rate, integrated selective oxide etch and nitride liner removal with high selectivity to corner nitride with the ability to remove the bottom nitride liner, and stripping of all polymer and photoresist.
6284149 High-density plasma etching of carbon-based low-k materials in a integrated circuit September 4, 2001
A plasma etching process for etching a carbon-based low-k dielectric layer in a multi-layer inter-level dielectric. The low-k dielectric may be divinyl siloxane-benzocyclobutene (BCB), which contains about 4% silicon, the remainder being carbon, hydrogen, and a little oxygen. The BCB etc
6238588 High pressure high non-reactive diluent gas content high plasma ion density plasma oxide etch pr May 29, 2001
The invention is embodied in a method of processing a semiconductor workpiece in a plasma reactor chamber, including supplying a polymer and etchant precursor gas containing at least carbon and fluorine into the chamber at a first flow rate sufficient of itself to maintain a gas pres
6211092 Counterbore dielectric plasma etch process particularly useful for dual damascene April 3, 2001
A dielectric etch process particularly applicable to forming a dual-damascene interconnect structure by a counterbore process, in which a deep via is etched prior to the formation of a trench connecting two of more vias. A single metallization fills the dual-damascene structure. The
6183655 Tunable process for selectively etching oxide using fluoropropylene and a hydrofluorocarbon February 6, 2001
A plasma etch process, particularly applicable to a self-aligned contact etch or other advanced structures requiring high-selectivity to nitride or other non-oxide materials and producing no etch stop. The process is preferably performed in a high-density plasma reactor for etching holes
6168726 Etching an oxidized organo-silane film January 2, 2001
A process for etching an oxidized organo-silane film exhibiting a low dielectric constant and having a most preferred atomic composition of 52% hydrogen, 8% carbon, 19% silicon, and 21% oxygen. The process of etching deep holes in the organo-silane film while stopping on a nitride or oth
6074959 Method manifesting a wide process window and using hexafluoropropane or other hydrofluoropropane June 13, 2000
A plasma etch process, particularly applicable to a self-aligned contact etch or other advanced structures requiring high-selectivity to nitride or other non-oxide materials and no etch stop. The process is preferably performed in a high-density plasma reactor for etching holes with eith
5965035 Self aligned contact etch using difluoromethane and trifluoromethane October 12, 1999
An oxide etch process that is highly selective to nitride, thereby being beneficial for a self-aligned contact etch of silicon dioxide to an underlying thin layer of silicon nitride. The process uses difluoromethane (CH.sub.2 F.sub.2) for its strong polymer forming and a greater amount o
5583737 Electrostatic chuck usable in high density plasma December 10, 1996
An electrostatic chuck for holding a wafer in a plasma processing chamber, the chuck including a pedestal having a top surface, an internal manifold for carrying a cooling gas, and a first plurality of holes leading from the internal manifold toward said top surface; and a dielectric lay
5560780 Protective coating for dielectric material on wafer support used in integrated circuit processin October 1, 1996
Improvements in a wafer support apparatus used for electrostatic clamping of a wafer to the wafer support, and a method of making same, are disclosed wherein a dielectric material, formed on the surface of a wafer support facing the wafer to facilitate the electrostatic clamping, has a
5539609 Electrostatic chuck usable in high density plasma July 23, 1996
An electrostatic chuck for holding a wafer in a plasma processing chamber, the chuck including a pedestal having a top surface, an internal manifold for carrying a cooling gas, and a first plurality of holes leading from the internal manifold toward said top surface; and a dielectric lay
5491603 Method of determining a dechucking voltage which nullifies a residual electrostatic force betwee February 13, 1996
The invention is embodied in a method of determining an optimum de-chucking voltage for nullifying residual electrostatic forces on a wafer in an electrostatic chuck for removal of the wafer from the chuck, including holding the wafer on the electrostatic chuck by applying an electrostat










 
 
  Recently Added Patents
Electronic device and control method therein
Vehicle fender
Method and apparatus for selective decoding in a wireless communication system
Stool
Evaluating programmer efficiency in maintaining software systems
Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor
Printed circuit board unit having routing unit mounted thereon and computer device having the same
  Randomly Featured Patents
Display rack with TV monitor for flooring samples
System and method of incorporating user preferences in image searches
Bullet nose filler for improved lethality
Cyclosporin analogues and their pharmaceutical uses
Quality rating function for a discrete decoded picture
System and method for a payment system directory
Data signal handling circuitry and methods with error analysis capabilities
Asymmetric channel doping for improved memory operation for floating body cell (FBC) memory
Oxidation and fatigue resistant metallic coating
Method of collection and linking of positional data from satellite localization and other data