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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Dillon; Michael N.
Address:
Richfield, MN
No. of patents:
12
Patents:












Patent Number Title Of Patent Date Issued
8166440 Basic cell architecture for structured application-specific integrated circuits April 24, 2012
A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by form
7760578 Enhanced power distribution in an integrated circuit July 20, 2010
An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails
7404154 Basic cell architecture for structured application-specific integrated circuits July 22, 2008
A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by form
7269803 System and method for mapping logical components to physical locations in an integrated circuit September 11, 2007
A system and method for mapping Intellectual Property (IP) components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a legal location for the IP
7233540 Latch-based random access memory (LBRAM) with tri-state banking and contention avoidance June 19, 2007
A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an
7231625 Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design June 12, 2007
A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Eac
7216323 Process for designing base platforms for IC design to permit resource recovery and flexible macr May 8, 2007
Base platforms customizable into ICs are designed by identifying a plurality of macros for placement on the platform, each macro being defined in part by a plurality of elements that perform respective functions of the macro. Identical elements in a plurality of macros are identified
6934171 Semiconductor integrated circuit having voltage-down circuit regulator and charge sharing August 23, 2005
An integrated circuit is provided, which includes first, second and third power supply conductors. The second power supply conductor has a higher voltage than the first power supply conductor, and the third power supply conductor has a higher voltage than the second power supply conducto
6800882 Multiple-bit memory latch cell for integrated circuit gate array October 5, 2004
A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transi
6748579 Method of using filler metal for implementing changes in an integrated circuit design June 8, 2004
A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask
6559701 Method to reduce power bus transients in synchronous integrated circuits May 6, 2003
A method of reducing power rail transients on integrated circuits. The power rail transients are reduced by controlling clock skew in a manner which minimizes dI/dT current demands. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out th
6093214 Standard cell integrated circuit layout definition having functionally uncommitted base cells July 25, 2000
A method of forming a layout definition of a semiconductor integrated circuit includes generating a netlist of functionally committed standard cell instances and the electrical interconnections between the standard cell instances. The standard cell instances are then placed in a layout










 
 
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