| Patent Number |
Title Of Patent |
Date Issued |
| 5635858 |
Zero-stopping incrementers |
June 3, 1997 |
| A zero-stopping incrementer operates on the recognition that half of all digital values that require incrementing will be even numbers; that is, the least significant bit (LSB) is a binary "0". Incrementing such a number merely requires changing the LSB from a binary "0" to a binary "1". |
| 5541887 |
Multiple port cells with improved testability |
July 30, 1996 |
| Sequentially terminated write enable pulses applied to respective input ports of a multi-port memory cell is effective to establish a priority among those input ports and provide unconditionally unambiguous writing to a memory cell when write operations are concurrently attempted at two |
| 5483179 |
Data output drivers with pull-up devices |
January 9, 1996 |
| A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, |
| 5453953 |
Bandgap voltage reference generator |
September 26, 1995 |
| A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will |
| 5451535 |
Method for manufacturing a memory cell |
September 19, 1995 |
| A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a m |
| 5418477 |
Data output buffer pull-down circuit for TTL interface |
May 23, 1995 |
| A pull-down circuit for a TTL compatible data output buffer uses NMOS devices. The pull-down circuit comprising two NMOS stages. Namely, a diode configuration stage where the gate and drain electrodes are shorted together during pull-down and a common-source stage. Both PMOS and NMOS |
| 5362663 |
Method of forming double well substrate plate trench DRAM cell array |
November 8, 1994 |
| A high density substrate plate DRAM cell memory device and process are described in which a buried well region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The |
| 5359552 |
Power supply tracking regulator for a memory array |
October 25, 1994 |
| A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will |
| 5343092 |
Self-biased feedback-controlled active pull-down signal switching |
August 30, 1994 |
| High speed, low power signal switching logic implementable in bipolar or BiCMOS technology is described. Signal switching is between a first prescribed state and a second prescribed state and is accomplished using a conventional active signal pull-up circuit in combination with a novel |
| 5339274 |
Variable bitline precharge voltage sensing technique for DRAM structures |
August 16, 1994 |
| A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in |
| 5336629 |
Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such |
August 9, 1994 |
| A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has |
| 5331189 |
Asymmetric multilayered dielectric material and a flash EEPROM using the same |
July 19, 1994 |
| A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a m |
| 5321647 |
Semiconductor memory device and operational method with reduced well noise |
June 14, 1994 |
| A semiconductor memory device and operational method having reduced well noise are provided. The memory device includes a plurality of memory cells arranged in rows and columns within an array well and addressable by a plurality of word lines and bit lines. The array well is biased to a |
| 5300800 |
Low leakage substrate plate DRAM cell |
April 5, 1994 |
| Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor disposed in a trench formed in a semiconductor substrate and an access transistor disposed in a well which is opposite in conductivity type to that of the substrate and a buried oxide collar which |
| 5292678 |
Forming a bit line configuration for semiconductor memory |
March 8, 1994 |
| A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in |
| 5289432 |
Dual-port static random access memory cell |
February 22, 1994 |
| A dual port SRAM is shown which comprises first and second word lines and first and second bit lines. A pair of semiconductor memory devices are cross coupled into a bistable circuit for storing true and complement logic levels and are coupled between common and power supply lines. A |
| 5280452 |
Power saving semsing circuits for dynamic random access memory |
January 18, 1994 |
| A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines, one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier in the sensing circuit is latched, the sense amplifier includes first |
| 5268871 |
Power supply tracking regulator for a memory array |
December 7, 1993 |
| A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will |
| 5257232 |
Sensing circuit for semiconductor memory with limited bitline voltage swing |
October 26, 1993 |
| A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sens |
| 5253202 |
Word line driver circuit for dynamic random access memories |
October 12, 1993 |
| A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the wordlines to a negative potential with respect to the substrate, thereby decreasing the access time. An NMOS pull-down transis |
| 5250829 |
Double well substrate plate trench DRAM cell array |
October 5, 1993 |
| A high density substrate plate DRAM cell memory device and process are described in which a buried well region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The |
| 5214603 |
Folded bitline, ultra-high density dynamic random access memory having access transistors stacke |
May 25, 1993 |
| A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has |
| 5212616 |
Voltage regulation and latch-up protection circuits |
May 18, 1993 |
| An improved latch-up protection circuit is disclosed which prevents damage to a CMOS integrated circuit chip due to transient surges or internal-circuitry initiated latch-ups and which clears any latch-up condition or SCR mode. In each embodiment, the latch-up protection circuit is i |
| 5204280 |
Process for fabricating multiple pillars inside a dram trench for increased capacitor surface |
April 20, 1993 |
| A method is disclosed for fabricating a DRAM trench capacitor with multiple-pillars inside the trench for increased surface area.A thin pad oxide of a few tens of nonometers is grown on a silicon substrate. A layer of silicon nitride is deposited and another layer of oxide is then deposi |
| 5185719 |
High speed dynamic, random access memory with extended reset/precharge time |
February 9, 1993 |
| A computer system is described which includes a DRAM having a plurality of memory cells arranged in rows and columns. The system includes a row address buffer, and circuitry for generating a row address strobe signal that exhibits both active and inactive levels during each DRAM memory |
| 5170243 |
Bit line configuration for semiconductor memory |
December 8, 1992 |
| A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in |
| 5162668 |
Small dropout on-chip voltage regulators with boosted power supply |
November 10, 1992 |
| Novel boosted power supplies are disclosed for an internal, on-chip regulator circuit which includes a differential amplifier coupler to a series regulating element operating as a source follower, and in which a voltage pump circuit is provided to generate a boosted power supply for |
| 5157634 |
DRAM having extended refresh time |
October 20, 1992 |
| A DRAM is described including a plurality of operable storage cells, each cell including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a mi |
| 5144165 |
CMOS off-chip driver circuits |
September 1, 1992 |
| Output driver circuits which do not require two stacked PMOS pull-up transistors in order to interface a lower on-chip supply voltage with a higher voltage off-chip bus provide a significant savings in chip area for DRAMs. According to a first embodiment, an on-chip pump circuit generate |
| 5107459 |
Stacked bit-line architecture for high density cross-point memory cell array |
April 21, 1992 |
| A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line intercon |
| 5075571 |
PMOS wordline boost cricuit for DRAM |
December 24, 1991 |
| A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure having one contact coupled to a wordline, a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well about the gate, first a |
| 5034787 |
Structure and fabrication method for a double trench memory cell device |
July 23, 1991 |
| A method is described for fabricating a novel double trench memory structure including a shallow trench access transistor adjacent to a deep trench storage capacitor. The described three-dimensional DRAM cell structure consists of shallow trench access transistors and deep trench sto |
| 5021355 |
Method of fabricating cross-point lightly-doped drain-source trench transistor |
June 4, 1991 |
| A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed arou |
| 4999518 |
MOS switching circuit having gate enhanced lateral bipolar transistor |
March 12, 1991 |
| Circuitry for implementing a gate enhanced lateral transistor to provide a circuit having a bipolar current driving capability and an FET channel voltage drop. The circuits provide switching of the lateral transistor by enabling both gate and base connections. The device is merged into a |
| 4988637 |
Method for fabricating a mesa transistor-trench capacitor memory cell structure |
January 29, 1991 |
| A method is described for fabricating a DRAM cell in a monocrystalline substrate wherein the cell includes an FET transistor and a capacitor. The method includes the steps of providing a buried storage capacitor in a trench in the substrate; forming a semiconductor mesa area juxtaposed t |
| 4954854 |
Cross-point lightly-doped drain-source trench transistor and fabrication process therefor |
September 4, 1990 |
| A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed arou |
| 4954731 |
Wordline voltage boosting circuits for complementary MOSFET dynamic memories |
September 4, 1990 |
| Two embodiments of a wordline boost clock circuit that can be used in high speed DRAM circuits are disclosed. The clock circuits require only one boost capacitor and discharge the wordlines faster, improving the DRAM access time. The basic feature of the clock circuit is in the floating |
| 4927779 |
Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memor |
May 22, 1990 |
| A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor dev |
| 4922128 |
Boost clock circuit for driving redundant wordlines and sample wordlines |
May 1, 1990 |
| A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected |
| 4920065 |
Method of making ultra dense dram cells |
April 24, 1990 |
| This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a |
| 4910709 |
Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memor |
March 20, 1990 |
| A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor dev |
| 4894697 |
Ultra dense dram cell and its method of fabrication |
January 16, 1990 |
| This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a |
| 4816706 |
Sense amplifier with improved bitline precharging for dynamic random access memory |
March 28, 1989 |
| A novel sense amplifier and decoupling device structure for integrated circuit memories wherein an embodiment of a cross-coupled sense amplifier includes two PMOS devices, the gates of which devices are grounded and clamp the downward voltage swing of the memory bitlines to the absolute |
