| Patent Number |
Title Of Patent |
Date Issued |
| 7113969 |
Formatting denormal numbers for processing in a pipelined floating point unit |
September 26, 2006 |
| A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an |
| 6965906 |
Converting negative floating point numbers to integer notation without two's complement hardware |
November 15, 2005 |
| For use in a processor having integer and floating point execution cores, logic circuitry for, and a method of, converting negative numbers from floating point notation to integer notation. In one embodiment, the logic circuitry includes: (1) a shifter that receives a number in floating |
| 6954912 |
Error detection in dynamic logic circuits |
October 11, 2005 |
| Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones genera |
| 6801924 |
Formatting denormal numbers for processing in a pipelined floating point unit |
October 5, 2004 |
| A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an |
| 6757812 |
Leading bit prediction with in-parallel correction |
June 29, 2004 |
| For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receive |
| 6721772 |
Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls |
April 13, 2004 |
| For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system |
| 6654774 |
Generation of sign extended shifted numerical values |
November 25, 2003 |
| A computer-implemented method and system for performing an arithmetic shift right by n of an m-bit negative number. A right shifter executes a logical shift right operation on the number to be shifted. A left shifter performs a left shift on an m-bit mask of ones, left shifting the mask |
| 6523050 |
Integer to floating point conversion using one's complement with subsequent correction to elimin |
February 18, 2003 |
| For use in a processor having a floating point execution core, logic circuitry for, and a method of, converting negative numbers from integer notation to floating point notation. In one embodiment, the logic circuitry includes: (1) a one's complementer that receives a number in integ |
| 6490606 |
Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls |
December 3, 2002 |
| For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system |
| 6415308 |
Converting negative floating point numbers to integer notation without two's complement hardware |
July 2, 2002 |
| For use in a processor having integer and floating point execution cores, logic circuitry for, and a method of, converting negative numbers from floating point notation to integer notation. In one embodiment, the logic circuitry includes: (1) a shifter that receives a number in floating |
| 6405232 |
Leading bit prediction with in-parallel correction |
June 11, 2002 |
| For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receive |
