| Patent Number |
Title Of Patent |
Date Issued |
| 6980458 |
Sensing circuit for ferroelectric non-volatile memories |
December 27, 2005 |
| A circuit for sensing a ferroelectric non-volatile information storage unit comprises a pre-charge circuit for applying a prescribed pre-charge voltage to a storage capacitor of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the st |
| 6930907 |
FeRAM semiconductor memory |
August 16, 2005 |
| A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local |
| 6909626 |
Method and related circuit for accessing locations of a ferroelectric memory |
June 21, 2005 |
| A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective |
| 6872996 |
Method of fabricating a ferroelectric stacked memory cell |
March 29, 2005 |
| The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a |
| 6650147 |
Sense amplifier with extended supply voltage range |
November 18, 2003 |
| A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes |
| 6466059 |
Sense amplifier for low voltage memories |
October 15, 2002 |
| A sense amplifier of the type coupled to a reference bit line and at least one cell array bit line. The sense amplifier includes an amplifying stage and a current voltage conversion circuit that compare a reference current from the reference bit line and a cell current from the cell arra |
| 6011717 |
EEPROM memory programmable and erasable by Fowler-Nordheim effect |
January 4, 2000 |
| An EEPROM is organized in matrix form in word lines and bit lines. Storage cells are placed at the intersections of these lines. The cells include floating gate storage transistors. Groups of cells having separate bit lines but sharing a word line are created. Each group is connected to |
| 5841314 |
Charge pump type of negative voltage generator circuit and method |
November 24, 1998 |
| Disclosed is a charge pump type of negative voltage generator circuit, constructed on a P type substrate and supplying a negative voltage at one output by the pumping of negative charges in n series-connected pumping cells, n being an integer, these pumping cells including P type tra |
| 5796297 |
Selector switch circuit enabling the selective supply of voltages with different signs |
August 18, 1998 |
| A selector switch circuit comprises an input terminal to receive a positive voltage, an input terminal to receive a negative voltage, a command input terminal to receive a first command logic signal and an output terminal to provide an output voltage. The output is connected selectively |
| 5760638 |
Phase generator circuit for charge pump type or negative supply circuit |
June 2, 1998 |
| A phase generator circuit cyclically produces a first pair of phase signals and a second pair of phase signals, comprising a first circuit to produce a first phase of each pair of phase signals, these first phase signals being non-overlapping and switching over between a voltage 0 and a |
| 5652720 |
Electrically programmable memory with improved retention of data and a method of writing data in |
July 29, 1997 |
| The present invention concerns an electrically programmable memory and a method for writing within this memory. In order to avoid the degradation of information in a memory cell following a number of write cycles in the other cells of the same row, the present invention includes a sequen |
