| Patent Number |
Title Of Patent |
Date Issued |
| 7566922 |
Field effect transistor with suitable source, drain and channel materials and integrated circuit |
July 28, 2009 |
| The normally on transistor comprises a source, a drain and a channel. The source, drain and channel materials are chosen such that, for a NMOS type transistor, the electronic affinity of the drain material is lower than the electronic affinity of the channel material and the electronic |
| 7553693 |
Method for making a field effect transistor with diamond-like carbon channel and resulting trans |
June 30, 2009 |
| The field effect transistor comprises a source and a drain connected by a channel controlled by a gate electrode separated from the channel by a gate insulator. The channel is formed by a diamond-like carbon layer. The method for making the transistor successively comprises deposition of |
| 7466019 |
Rectangular semi-conducting support for microelectronics and method for making same |
December 16, 2008 |
| The semi-conducting support comprises a graphite substrate having a front surface and a rear surface and at least a first stack arranged on the front surface of the substrate. The first stack successively comprises a single-crystal diamond layer, an electrically insulating oxide layer an |
| 7425509 |
Method for forming patterns aligned on either side of a thin film |
September 16, 2008 |
| A method for forming patterns which are aligned on either side of a thin film deposited on a substrate. The method includes depositing a first pattern layer on the thin film which may occur before or after the local etching of the thin film to form a first marking. The method includes |
| 7425496 |
Method for delineating a conducting element disposed on an insulating layer, device and transist |
September 16, 2008 |
| A conducting layer is deposited on an insulating layer disposed on a substrate. A mask is formed on at least one area of the conducting layer, thus delineating in the conducting layer at least one complementary area not covered by the mask. The complementary areas of the conducting layer |
| 7022562 |
Field-effect transistor with horizontal self-aligned gates and the production method therefor |
April 4, 2006 |
| A field-effect transistor including: a support substrate, an active area forming a channel; a first active gate which is associated with a first face of the active area; source and drain areas which are formed in the active area and which are self-aligned on the first gate; a second |
| 6998310 |
Processes for making a single election transistor with a vertical channel |
February 14, 2006 |
| This invention relates to a process for a manufacturing a Coulomb blockade transistor. The process comprises the following steps in sequence: deposition on an insulating substrate of a source layer, a tunnel-insulating layer and an alternating stack of at least one conducting layer a |
| 6955963 |
Damascene architecture electronic storage and method for making same |
October 18, 2005 |
| An electronic memory having a source (118) and a drain (120) comprising on a substrate (100) a floating gate (260) and a control gate (264).According to the invention, the floating gate (260) has a substantially U-shaped cross-section defining a space within which the control gate (264) |
| 6867128 |
Method for making an electronic component with self-aligned drain and gate, in damascene archite |
March 15, 2005 |
| A method for fabricating an electronic component with a self-aligned source, drain and gate. The method includes forming a dummy gate on a silicon substrate, in which the dummy gate defines a position for a channel of the component. The method also includes at least one implantation |
| 6787845 |
Metal source and drain mos transistor |
September 7, 2004 |
| MOS transistor comprising: a channel region (120) made of a semiconducting material above which there is a grid structure, the grid structure comprising a grid (110) and insulating spacers (122) coating the sides of the grid, regions called source and drain extension regions (116a, 118 |
| 6727179 |
Method for creating an integrated circuit stage wherein fine and large patterns coexist |
April 27, 2004 |
| Successive use is made of a layer of radiation-sensitive resin at points intended to form wide semi-conductor patterns in a still intact layer, under at least one hard mask, then of a resin sensitive to particle bombardment over fine patterns to be formed in this same layer, which may |
| 6562687 |
MIS transistor and method for making same on a semiconductor substrate |
May 13, 2003 |
| The invention relates to an MIS transistor comprising a channel region (118), source (114) and drain (116) regions arranged on either side of the channel, and a gate (150) set closely above the channel region. According to the invention, the channel has a doped central part (140), locate |
| 6150241 |
Method for producing a transistor with self-aligned contacts and field insulation |
November 21, 2000 |
| A process for making a MOS transistor. The transistor includes a source, a channel and drain formed on a portion of silicon film in a silicon-on-insulator type structure. A field insulation layer surrounds the film. A grid structure with insulated flanks is formed above the channel. |
| 6091076 |
Quantum WELL MOS transistor and methods for making same |
July 18, 2000 |
| A new quantum well MOS transistor is described along with a processes for manufacturing it. In this transistor, the source and drain areas are separated from the channel by sufficiently thin insulating layers to enable the passage of charge carriers by the tunnel effect. Each of the |
| 5973365 |
MOS transistor and lateral insulating method of a MOS transistor active region |
October 26, 1999 |
| A MOS type field effect transistor including a portion of silicon layer (114) forming an active region (114a) placed between a grid oxide layer (120) and a buried oxide layer (112), and laterally delimited by lateral oxide insulation blocks (116). The portion of the silicon layer (114) h |
| 5913136 |
Process for making a transistor with self-aligned source and drain contacts |
June 15, 1999 |
| The invention relates to a process for making a transistor with self-aligned contact points and comprises the following steps: formation of multiple layers on a substrate (100) and etching of the multiple layers using a first mask, but preserving a column of the multiple layer; forma |
| 5897939 |
Substrate of the silicon on insulator type for the production of transistors and preparation pro |
April 27, 1999 |
| Process for the preparation of a substrate of the silicon on insulator type for the production of transistors. The process comprises the following stages:a) shaping the surface of a silicon substrate (10) in order to define a first region (20) and a second region (22) forming a depressio |
| 5314832 |
Process for the production of a high voltage MIS integrated circuit |
May 24, 1994 |
| A process for the production of a high voltage, MIS integrated circuit or a substrate incorporating double implantation MIS transistors creates transistors whose sources and drains consist of double junctions and whose gates are formed in a semiconducting layer. The initial process inclu |
