| Patent Number |
Title Of Patent |
Date Issued |
| 6336170 |
Method and system in a distributed shared-memory data processing system for determining utilizat |
January 1, 2002 |
| A method and system in a distributed shared-memory data processing system are disclosed having a single operating system being executed simultaneously by a plurality of processors included within a plurality of coupled processing nodes for determining a utilization of each memory loc |
| 6266745 |
Method and system in a distributed shared-memory data processing system for determining utilizat |
July 24, 2001 |
| A method and system in a distributed shared-memory data processing system are disclosed for determining a utilization of each of a plurality of coupled processing nodes by one of a plurality of executed threads. The system includes a single operating system being executing simultaneously |
| 5603041 |
Method and system for reading from a m-byte memory utilizing a processor having a n-byte data bu |
February 11, 1997 |
| A method and system are disclosed for reading data from an m-byte memory device utilizing a processor having an n-byte data bus, where m is less than or equal to n, which do not require the processor to support special bus cycles, bus select signals, or dynamic bus sizing. Responsive to |
| 5553276 |
Self-time processor with dynamic clock generator having plurality of tracking elements for outpu |
September 3, 1996 |
| A method and system are provided for self-timed processing. An operation is executed with a functional unit. A timing of the operation execution is simulated with a tracking element, and a tracking signal is output. A sequencing signal is varied to the functional unit in response to the |
| 5548746 |
Non-contiguous mapping of I/O addresses to use page protection of a process |
August 20, 1996 |
| A system and method for protecting individual segments of a contiguous I/O address space on a system bus using the page access protection resources of a processor operating on a processor bus address space. The contiguous I/O address space is segmented and mapped by translation into the |
| 5544342 |
System and method for prefetching information in a processing system |
August 6, 1996 |
| A method and system are provided for prefetching information in a processing system. A first memory has multiple first locations. At least one of the first locations stores information including an address of a different first location, the different first location having been refere |
| 5448521 |
Connecting a short word length non-volatile memory to a long word length address/data multiplexe |
September 5, 1995 |
| A system and method for connecting a short word length memory to a significantly wider bus operated in an address/data multiplexing mode. A mode of operation is defined for the bus whereby the bus lines are divided for purposes of memory accessing into a data group and an address group. |
