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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Dean; Jeffrey
Address:
Menlo Park, CA
No. of patents:
21
Patents:




Patent Number Title Of Patent Date Issued
7386616 System and method for providing load balanced processing June 10, 2008
A system and method for providing load balanced processing is described. One or more files selected from a set of files are logically duplicated. At least one file and at least one logically duplicated file, is stored at one of a plurality of servers as specified in a load balancing layo
7308643 Anchor tag indexing in a web crawler system December 11, 2007
Provided is a method and system for indexing documents in a collection of linked documents. A link log, including one or more pairings of source documents and target documents is accessed. A sorted anchor map, containing one or more target document to source document pairings, is gen
7254580 System and method for selectively searching partitions of a database August 7, 2007
When a search query is received, a plurality of partition indexes are searched using the set of search terms in the search query. Each partition index corresponds to a partition of a document index. The search of each respective partition index identifies a subset of a plurality of d
7174346 System and method for searching an extended database February 6, 2007
Once a search query is received from a user, a standard index is searched based on the search query. The standard index forms part of a set of replicated standard indexes having multiple instances of the standard index. A signal is then determined based on the search of the standard
6665837 Method for identifying related pages in a hyperlinked database December 16, 2003
A method is described for identifying related pages among a plurality of pages in a linked database such as the World Wide Web. An initial page is selected from the plurality of pages. Pages linked to the initial page are represented as a graph in a memory. The pages represented in the g
6487555 Method and apparatus for finding mirrored hosts by analyzing connectivity and IP addresses November 26, 2002
A method and system that detects mirrored host pairs using information about a large set of pages, including one or more of: URLs, IP addresses, and connectivity information. The identities of the detected mirrored hosts are then saved so that browsers, crawlers, proxy servers, or the
6321220 Method and apparatus for preventing topic drift in queries in hyperlinked environments November 20, 2001
A method and apparatus for preventing topic drift in queries in hyperlinked environments uses equivalence components for ranking pages containing information that is relevant to the topic of a user query input to a search engine. The method includes the step of providing a query to a
6286006 Method and apparatus for finding mirrored hosts by analyzing urls September 4, 2001
A method and apparatus that detects mirrored host pairs using information about a large set of pages, including URLs. The identities of the detected mirrored hosts are then saved so that browsers, crawlers, proxy servers, or the like can correctly identify mirrored web sites. The describ
6237073 Method for providing virtual memory to physical memory page mapping in a computer operating syst May 22, 2001
A method is provided for guiding virtual-to-physical mapping policies in a computer system including a processor and a memory. State information is randomly sampled from selected memory references in a stream of memory references issued by the processor to the memory. Cache hit/miss stat
6195748 Apparatus for sampling instruction execution information in a processor pipeline February 27, 2001
An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. E
6175814 Apparatus for determining the instantaneous average number of instructions processed January 16, 2001
An apparatus is provided for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock. The number of instructions entering a particular stage of the pipeline are stored in a queue during each of
6163840 Method and apparatus for sampling multiple potentially concurrent instructions in a processor pi December 19, 2000
An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A
6148396 Apparatus for sampling path history in a processor pipeline November 14, 2000
An apparatus is provided for collecting state information associated with an execution path of recently processed instructions in a processor pipeline of a computer system. The apparatus identifies a class of instructions to be sampled. Path-identifying state information of a current
6138113 Method for identifying near duplicate pages in a hyperlinked database October 24, 2000
A method is described for identifying pages that are near duplicates in a linked database. In the linked database, pages can have incoming links and outgoing links. Two pages are selected, a first page and a second page. For each selected page, the number of outgoing links is determined.
6119075 Method for estimating statistics of properties of interactions processed by a processor pipeline September 12, 2000
Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A set of instructions are r
6092180 Method for measuring latencies by randomly selected sampling of the instructions while the instr July 18, 2000
In a method for scheduling instructions executed in a computer system including a processor and a memory subsystem, pipeline latencies and resource utilization are measured by sampling hardware while the instructions are executing. The instructions are then scheduled according to the
6070009 Method for estimating execution rates of program execution paths May 30, 2000
A method is provided for estimating execution rates of program executions paths. The method samples path-identifying state information of selected instructions while executing the program in a processor. A control flow graph of the program is supplied, the control flow graph includes a
6000044 Apparatus for randomly sampling instructions in a processor pipeline December 7, 1999
An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are iden
5964867 Method for inserting memory prefetch operations based on measured latencies in a program optimiz October 12, 1999
A method is provided for optimizing a program by inserting memory prefetch operations in the program executing in a computer system. The computer system includes a processor and a memory. Latencies of instructions of the program are measured by hardware while the instructions are process
5923872 Apparatus for sampling instruction operand or result values in a processor pipeline July 13, 1999
An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a par
5809450 Method for estimating statistics of properties of instructions processed by a processor pipeline September 15, 1998
A method is provided for estimating statistics of properties of instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Some of the fetched instructions are randomly


 
 
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