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Inventor:
Dastidar; Jayabrata Ghosh
Address:
Santa Clara, CA
No. of patents:
6
Patents:




Patent Number Title Of Patent Date Issued
7409669 Automatic test configuration generation facilitating repair of programmable circuits August 5, 2008
Techniques are provided that control the generation of test routes to improve the ability of a test system to isolate defects on programmable circuits. A test generator creates test routes that test the horizontal resources. In these test routes, the inputs of each circuit element are
7131043 Automatic testing for programmable networks of control signals October 31, 2006
Techniques are provided for testing routing resources that route control signals on programmable integrated circuits (ICs). Control signals (such as clock signals) are routed through a logic gate to a test register. Values of the control signals are stored in the test register, trans
7111213 Failure isolation and repair techniques for integrated circuits September 19, 2006
Techniques for isolating and repairing failures on a programmable circuit are provided. An error on programmable circuit may be caused by a defect on the chip. The error is located, and the circuit elements effected by the defect are isolated. By identifying operable circuit elements nea
7062685 Techniques for providing early failure warning of a programmable circuit June 13, 2006
Techniques for monitoring the performance of a programmable circuit and to provide an early warning of a potential failure are provided. A processor monitors the performance of components on a programmable circuit over time. The processor stores performance characteristics for the compon
7058534 Method and apparatus for application specific test of PLDs June 6, 2006
Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application
7024327 Techniques for automatically generating tests for programmable circuits April 4, 2006
Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmab


 
 
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