| Patent Number |
Title Of Patent |
Date Issued |
| 7606550 |
Method and system for a dual mode receiver with low intermediate frequency (IF) and zero second |
October 20, 2009 |
| In RF transceivers, a method and system for a dual mode receiver with low intermediate frequency (IF) and zero second IF are provided. An RF receivers may be adapted to operate in a low IF down conversion mode or a baseband down conversion mode. A control signal may be generated based on |
| 7596356 |
On-chip baseband-to-RF interface and applications thereof |
September 29, 2009 |
| An on-chip baseband-to-RF interface includes a receive/transmit section, a control section, and a clock section. The receive/transmit section, when in a receive mode, provides the stream of inbound symbols from the RF circuit to the baseband processing module and, when in a transmit mode |
| 7593707 |
Method and system for compensation of DC offset in an RF receiver |
September 22, 2009 |
| Aspects of compensating for DC offset in an RF receiver may comprise sampling data from at least one of a plurality of output paths, selecting a sampled data and generating at least one feedback signal based on the selected sampled data. The generated feedback signal may be fed back to |
| 7567628 |
Symmetric differential slicer |
July 28, 2009 |
| A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The |
| 7566994 |
Small-step, switchable capacitor |
July 28, 2009 |
| According to an example embodiment, an apparatus is provided that produces a small-step switchable capacitor, which can have steps that are smaller in value than the smallest capacitor used in the system. In one embodiment, an input signal is connected to a switchable capacitor system |
| 7551910 |
Translation and filtering techniques for wireless receivers |
June 23, 2009 |
| Various embodiments are disclosed relating to wireless receivers. According to an example embodiment, a method and apparatus are provided. The method may include receiving an input signal within a first frequency range (e.g., RF). The input signal may include a desired signal and a b |
| 7545889 |
Blocker performance in a radio receiver |
June 9, 2009 |
| Configuring a multiple stage band pass filter of a radio frequency receiver commences by setting a corner of a low pass mixer output filter that receives a down sampled analog information signal. Operation continues with setting a buffer output filter corner of a low pass buffer outp |
| 7541870 |
Cross-coupled low noise amplifier for cellular applications |
June 2, 2009 |
| Cross-coupled low noise amplifier for cellular applications. A circuitry implementation that includes two pairs of metal oxide semiconductor field-effect transistors (MOSFETs) (either N-type of P-type) operates as an LNA, which can be used within any of a wide variety of communication |
| 7505749 |
Method and system for a synthesizer/local oscillator generator (LOGEN) architecture for a quad-b |
March 17, 2009 |
| Methods and systems for processing signals for a multiband radio are disclosed herein. Aspects of the method may comprise dividing an input signal generated by an oscillator used to generate signals for each of a plurality of bands for the multiband radio. A feedback loop reference s |
| 7471142 |
Filter calibration with cell re-use |
December 30, 2008 |
| Various embodiments are disclosed relating filter calibration with cell re-use. According to an example embodiment, an apparatus includes a first circuit, including a variable circuit element. The first circuit is adapted to output an output frequency signal during a calibration mode |
| 7463176 |
DAC module and applications thereof |
December 9, 2008 |
| A digital to analog conversion (DAC) module includes a digital to analog converter, a sample and hold circuit, and a switch module. The digital to analog converter is coupled to convert a digital signal into an analog signal. The sample and hold circuit is coupled to sample the analog |
| 7450920 |
Method and system for compensation of DC offset in an RF receiver |
November 11, 2008 |
| Aspects of compensating for DC offset in an RF receiver may comprise sampling data from at least one of a plurality of output paths, selecting a sampled data and generating at least one feedback signal based on the selected sampled data. The generated feedback signal may be fed back to |
| 7429891 |
Method and system for low noise amplifier (LNA) gain adjustment through narrowband received sign |
September 30, 2008 |
| Methods and systems for processing a plurality of signals are disclosed herein. Aspects of the method may comprise amplifying an input signal. The amplified input signal may be bandpass filtered. Amplification of the input signal may be adjusted based on only narrowband received signal |
| 7421260 |
Method and system for a second order input intercept point (IIP2) correction |
September 2, 2008 |
| In RF transceivers, a method and system for a second order input intercept point (IIP2) correction are provided. A DC offset sensor may detect DC offset voltages produced by blocker signals in "I" and "Q" signal component paths in an RF receiver. The DC offset sensor may generate con |
| 7411381 |
Circuit calibration using a time constant |
August 12, 2008 |
| According to one general aspect, an apparatus includes a first resistor in a first current path of a resistor-capacitor (RC) circuit, the resistor connected to a power source. A variable capacitor is included in a second current path of the RC circuit and operably connected to the power |
| 7395098 |
Bias filtering module including MOS capacitors |
July 1, 2008 |
| A bias filtering module with at least two capacitive levels satisfies both a settle time requirement and a filtering requirement using a voltage dependent filter module whose capacitance is a function of a voltage potential on the filtering circuitry output terminal. The final capaci |
| 7389087 |
Adaptive radio transceiver with filtering |
June 17, 2008 |
| An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration in |
| 7375595 |
Method and apparatus for calibrating a phase locked loop in open-loop |
May 20, 2008 |
| Methods and apparatus for calibrating a transitional loop, such as a phase locked loop, are disclosed. An example method includes performing an open loop calibration of a voltage controlled oscillator (VCO). The open loop calibration includes tuning the output oscillation frequency of th |
| 7285993 |
Method and system for a divide by N circuit with dummy load for multiband radios |
October 23, 2007 |
| Certain embodiments of the invention provide a method and system for symmetrically loading a divider circuit for multiband receivers. The method may comprise coupling a second divider circuit to an I component output signal of a first divider circuit and coupling a dummy load to a Q |
| 7248081 |
Slicer with large input common mode range |
July 24, 2007 |
| A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an invert |
| 7196582 |
Method and system for low noise amplifier (LNA) and power amplifier (PA) gain control |
March 27, 2007 |
| Methods and systems for processing signals are disclosed herein. In one aspect of the invention a circuit for processing signals may comprise a triple well (TW) NMOS transistor coupled to an amplifier core. The TW NMOS transistor may track process and temperature variations (PVT) of at |
| 7109798 |
Method and system for common mode feedback circuitry for RF buffers |
September 19, 2006 |
| For a high frequency buffer, a high frequency output path may be isolated from a low frequency feedback path using a common mode feedback loop. The common mode feedback loop may be utilized to adjust an output DC level. The common mode feedback loop may comprise a first differential ampl |
| 7071790 |
Method and system for a differential switched capacitor array for a voltage controlled oscillato |
July 4, 2006 |
| Methods and systems for increasing an amplifier circuit's Q factor are disclosed herein. The method may comprise coupling a first LC tank to a source of a single switching transistor and coupling a second LC tank to a drain of the single switching transistor. A gate of the single swi |
