| Patent Number |
Title Of Patent |
Date Issued |
| 7602858 |
Digital transmitter |
October 13, 2009 |
| An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equaliz |
| 7602857 |
Digital transmitter |
October 13, 2009 |
| An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equaliz |
| 7580474 |
Digital transmitter |
August 25, 2009 |
| An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equaliz |
| 7564920 |
Digital transmitter |
July 21, 2009 |
| An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equaliz |
| 7529915 |
Context switching processor with multiple context control register sets including write address |
May 5, 2009 |
| Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one th |
| 7526046 |
Digital transmitter |
April 28, 2009 |
| An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equaliz |
| 7498882 |
Signaling system with low-power automatic gain control |
March 3, 2009 |
| An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within th |
| 7495513 |
Signaling system with low-power automatic gain control |
February 24, 2009 |
| An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within th |
| 7489739 |
Method and apparatus for data recovery |
February 10, 2009 |
| A method for recovering data includes oversampling an input data signal to provide sample sets, and storing a plurality of sample sets in addressable memory. The sample sets are processed, using sequential logic to make determinations of respective samples suitable for use in data re |
| 7460565 |
Data communications circuit with multi-stage multiplexing |
December 2, 2008 |
| In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely |
| 7414489 |
Phase controlled oscillator circuit with input signal coupler |
August 19, 2008 |
| An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in |
| 7408959 |
Method and apparatus for ensuring cell ordering in large capacity switching systems and for sync |
August 5, 2008 |
| Where links between a port module and plural switch fabric slices are of various lengths, a cell is transmitted from the port module to a switch fabric slice in response to a grant. The transmission is delayed by an amount based on a link round trip delay (RTD) value for the correspondin |
| 7401205 |
High performance RISC instruction set digital signal processor having circular buffer and loopin |
July 15, 2008 |
| A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instructi |
| 7301941 |
Multistage digital cross connect with synchronized configuration switching |
November 27, 2007 |
| A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized |
| 7292594 |
Weighted fair share scheduler for large input-buffered high-speed cross-point packet/cell switch |
November 6, 2007 |
| A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input cre |
| 7292580 |
Method and system for guaranteeing quality of service in a multi-plane cell switch |
November 6, 2007 |
| Data cells of plural classes are transferred from input ports to output ports through a switch by storing the cells at each input port in class-specific virtual output queues (VOQ) within sets of VOQs associated with output ports, and providing credits to VOQs according to class-asso |
| 7260092 |
Time slot interchanger |
August 21, 2007 |
| A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized |
| 7257183 |
Digital clock recovery circuit |
August 14, 2007 |
| A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts |
| 7216214 |
System and method for re-ordering memory references for access to memory |
May 8, 2007 |
| A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active loc |
| 7187721 |
Transition-time control in a high-speed data transmitter |
March 6, 2007 |
| Transition time of a data signal is controlled by applying different delays to the data signal and combining the delayed data signals. The transition time of the data output is determined by difference in delays applied to the data input and may be proportional to bit time of the bit |
| 7187679 |
Internet switch router |
March 6, 2007 |
| An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface |
| 7162615 |
Data transfer bus communication using single request to perform command and return data to desti |
January 9, 2007 |
| Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to send a separate request for the result. In accordance with the systems and methods, a bus |
| 7130847 |
Prefix search method |
October 31, 2006 |
| Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each se |
| 7100026 |
System and method for performing efficient conditional vector operations for data parallel archi |
August 29, 2006 |
| A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full proce |
| 7099404 |
Digital transmitter |
August 29, 2006 |
| An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equaliz |
| 7078979 |
Phase controlled oscillator circuit with input signal coupler |
July 18, 2006 |
| An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in |
| 7047391 |
System and method for re-ordering memory references for access to memory |
May 16, 2006 |
| A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active loc |
| 7043562 |
Irregular network |
May 9, 2006 |
| Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backplane are connected i |
| 6976064 |
Apparatus and methods for connecting modules using remote switching |
December 13, 2005 |
| A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths t |
| 6965299 |
High-speed, low-power crossbar switch |
November 15, 2005 |
| In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in |
| 6952431 |
Clock multiplying delay-locked loop for data communications |
October 4, 2005 |
| In a communications system, data is multiplexed onto a transmission medium at a transmitter and demultiplexed from the transmission medium at a receiver. The clock applied to the transmitter and receiver is a multiplying delay-locked loop in which a delay line provides a multiplied c |
| 6937073 |
Frequency multiplier with phase comparator |
August 30, 2005 |
| A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control th |
| 6934471 |
Photonic switch using time-slot interchange |
August 23, 2005 |
| An optical data stream is converted to electrical signals which are applied to a time-slot interchanger. The time-slot interchanger recorders the packets or cells of the data stream to correspond to the schedule of an optical switch. The time-slot interchanger may contain a plurality of |
| 6891834 |
Apparatus and method for packet scheduling |
May 10, 2005 |
| In a network router, a tree structure or a sorting network is used to compare scheduling values and select a packet to be forwarded from an appropriate queue. In the tree structure, each leaf represents the scheduling value of a queue and internal nodes of the structure represent win |
| 6870838 |
Multistage digital cross connect with integral frame timing |
March 22, 2005 |
| A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized |
| 6861916 |
Phase controlled oscillator circuit with input signal coupler |
March 1, 2005 |
| An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in |
| 6807186 |
Architectures for a single-stage grooming switch |
October 19, 2004 |
| A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslo |
| 6728240 |
Serial-link circuit including capacitive offset adjustment of a high-speed receiver |
April 27, 2004 |
| A serial link circuit includes a transmitter which multiplexes the circuit's input signals together and uses a single processing circuit to generate a multiplexed output to be transmitted. The multiplexing is done with a limited voltage swing prior to preamplification. In this way, clock |
| 6717942 |
Space-efficient source routing |
April 6, 2004 |
| The required length of a route descriptor in a source routing system is obtained by inserting an implied exit field, use of run-length encoding, and use of variable-length encoding. In the variable-length encoding, codes having lesser bits are reserved for preferred directions. Preferred |
| 6674772 |
Data communications circuit with multi-stage multiplexing |
January 6, 2004 |
| In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely |
| 6654381 |
Methods and apparatus for event-driven routing |
November 25, 2003 |
| A router routes data packets. The router includes input physical channels for incrementally receiving portions of the data packets, and output physical channels. The router further includes data buffers, coupled with the input and output physical channels, for storing the portions of the |
| 6617936 |
Phase controlled oscillator |
September 9, 2003 |
| An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in |
| 6614268 |
High-speed, low-power inter-chip transmission system |
September 2, 2003 |
| In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the |
| 6606656 |
Apparatus and methods for connecting modules using remote switching |
August 12, 2003 |
| A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths t |
| 6598145 |
Irregular network |
July 22, 2003 |
| Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backplane are connected in a |
| 6563831 |
Router with virtual channel allocation |
May 13, 2003 |
| An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface |
| 6542555 |
Digital transmitter with equalization |
April 1, 2003 |
| An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equaliz |
| 6522632 |
Apparatus and method for efficient prefix search |
February 18, 2003 |
| A list of prefix keys, including enclosing prefix key pairs, are stored in leaves of a tree structure. In the leaf nodes, a prefix search key is compared to a set of prefix keys to identify a longest matching prefix. Each leaf node includes a single result pointer to a block of results a |
| 6476656 |
Low-power low-jitter variable delay timing circuit |
November 5, 2002 |
| The timing circuit includes at least one delay element and its supply voltage is obtained from an active current source. The current source is a current mirror which is driven by a differential amplifier. The differential amplifier compares a voltage on the delay element supply line |
| 6430527 |
Prefix search circuitry and method |
August 6, 2002 |
| Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search |
