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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
D'Inverno; Dominique
Address:
Villeneuve-Loubet, FR
No. of patents:
28
Patents:












Patent Number Title Of Patent Date Issued
8190861 Micro-sequence based security model May 29, 2012
A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex se
8032891 Energy-aware scheduling of application execution October 4, 2011
A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodimen
7941790 Data processing apparatus, system and method May 10, 2011
A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code
7840784 Test and skip processor instruction having at least one register operand November 23, 2010
A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is "skipped." The test and skip i
7840782 Mixed stack-based RISC processor November 23, 2010
A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some
7716673 Tasks distribution in a multi-processor including a translation lookaside buffer shared between May 11, 2010
A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run
7634643 Stack register reference control bit in source operand of instruction December 15, 2009
A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The instruction causes the processor to perform a test using the immediate value and the contents of the register referenced in
7565385 Embedded garbage collection July 21, 2009
An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded
7543014 Saturated arithmetic in a processing unit June 2, 2009
In some embodiments a system comprises an overflow control bit, a programmable saturation control bit, a processing unit, and a saturation unit coupled to the processing unit. A selection unit may select the output of the processing unit or the output of the saturation unit based on
7496930 Accessing device driver memory in programming language representation February 24, 2009
In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the applica
7434021 Memory allocation in a multi-processor system October 7, 2008
A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated
7330937 Management of stack-based memory usage in a processor February 12, 2008
A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as either a cache or scra
7203797 Memory management of local variables April 10, 2007
A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative
7174194 Temperature field controlled scheduling for processing systems February 6, 2007
A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build s
7146613 JAVA DSP acceleration by byte-code optimization December 5, 2006
A digital system and method of operation is which the digital system has a processor with a virtual machine environment for interpretively executing instructions. First, a sequence of instructions is received (404) for execution by the virtual machine. The sequence of instructions is
7120715 Priority arbitration based on current task and MMU October 10, 2006
A digital system and method of operation is provided in which several processors (740(0) 740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory
7069415 System and method to automatically stack and unstack Java local variables June 27, 2006
A processor preferably comprises a processing core that generates memory addresses to access a memory and on which a plurality of methods operate, a cache coupled to the processing core, and a programmable register containing a pointer to a currently active method's set of local vari
7062304 Task based adaptative profiling and debugging June 13, 2006
A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build s
6996683 Cache coherency in a multi-processor system February 7, 2006
A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transa
6901521 Dynamic hardware control for energy management systems using task attributes May 31, 2005
A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scena
6889330 Dynamic hardware configuration for energy management systems using task attributes May 3, 2005
A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scena
6772326 Interruptible an re-entrant cache clean range instruction August 3, 2004
A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in
6769052 Cache with selective write allocation July 27, 2004
A digital system and method of operation is provided in which several processors (590n) are connected to a shared cache memory resource (500). A translation lookaside buffer (TLB) (310n) is connected to receive a request virtual address from each respective processor. A set of address
6760829 MMU descriptor having big/little endian bit to control the transfer data between devices July 6, 2004
A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and another portion of the initiator resources are little endian. The memory is segregated into a set of regions by a memory m
6751706 Multiple microprocessors with a shared cache June 15, 2004
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associat
6742104 Master/slave processing system with shared translation lookaside buffer May 25, 2004
A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses .mu.TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the .mu.TLB and shared TLB, acce
6742103 Processing system with shared translation lookaside buffer May 25, 2004
A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses .mu.TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the .mu.TLB and shared TLB, acce
6681297 Software controlled cache configuration based on average miss rate January 20, 2004
A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a level three (L3) physical memory. Each tag entry includes a task-ID qualifier field and a resource ID qualifier field. Data










 
 
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