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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Cummings; Steven D.
Address:
Boise, ID
No. of patents:
11
Patents:












Patent Number Title Of Patent Date Issued
7943505 Advanced VLSI metallization May 17, 2011
A four layer interconnect structure is disclosed which includes a bottom conductive reactive layer such as titanium, a conductive barrier layer, such as titanium nitride, a conductive layer, such as aluminum-copper alloy, and a top conductive barrier layer, such as titanium nitride. The
7271413 Semiconductor constructions September 18, 2007
The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor
7253102 Methods for forming and integrated circuit structures containing enhanced-surface-area conductiv August 7, 2007
An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor
7122425 Methods of forming semiconductor constructions October 17, 2006
The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor
6838714 Low leakage diodes, including photodiodes January 4, 2005
A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photo
6812112 Methods for forming and integrated circuit structures containing enhanced-surface-area conductiv November 2, 2004
An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor depo
6764943 Methods for forming and integrated circuit structures containing enhanced-surface-area conductiv July 20, 2004
An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor depo
6534335 Optimized low leakage diodes, including photodiodes March 18, 2003
A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photo
6482736 Methods for forming and integrated circuit structures containing enhanced-surface-area conductiv November 19, 2002
An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor depo
5371701 Stacked delta cell capacitor December 6, 1994
A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon
5321649 Stacked delta cell capacitor June 14, 1994
A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon










 
 
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