| Patent Number |
Title Of Patent |
Date Issued |
| 5530290 |
Large scale IC personalization method employing air dielectric structure for extended conductor |
June 25, 1996 |
| Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections |
| 5444015 |
Larce scale IC personalization method employing air dielectric structure for extended conductors |
August 22, 1995 |
| Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections |
| 5363550 |
Method of Fabricating a micro-coaxial wiring structure |
November 15, 1994 |
| A method of fabricating a micro-coaxial wiring structure comprises forming a first insulation layer and patterning a trench therein. A first conductive layer is formed on the first insulation layer and having a shape conforming to the insulation layer and lining the trench. A second |
| 4364166 |
Semiconductor integrated circuit interconnections |
December 21, 1982 |
| An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high conductivity and reduced overlap capacitance in multilayer integrated circuit devices. |
| 4329706 |
Doped polysilicon silicide semiconductor integrated circuit interconnections |
May 11, 1982 |
| An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high conductivity and reduced overlap capacitance in multilayer integrated circuit devices. |
| 4274105 |
MOSFET Substrate sensitivity control |
June 16, 1981 |
| The sensitivity of the threshold voltage in MOSFET devices to changes in substrate voltage may be reduced at a given temperature by the introduction of sufficiently deep energy level, low diffusivity impurities into the depletion region under the gate of the MOSFET. |
| 4180596 |
Method for providing a metal silicide layer on a substrate |
December 25, 1979 |
| A method for providing on a substrate a layer of a metal silicide such as molybdenum silicide and/or tantalum silicide and/or tungsten silicide and/or rhodium silicide which includes coevaporating silicon and the respective metal onto a substrate, and then heat treating the substrate to |
| 3936322 |
Method of making a double heterojunction diode laser |
February 3, 1976 |
| A method for improving the current confinement capacity of a double heterojunction laser by using a high energy implantation of oxygen in the regions of an injection laser surrounding the active region of such laser so as to make such regions semi-insulating. |
