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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Cranford, Jr.; Hayden C.
Address:
Cary, NC
No. of patents:
71
Patents:


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Patent Number Title Of Patent Date Issued
8219041 Design structure for transmitter bandwidth optimization circuit July 10, 2012
A design structure embodied in a machine-readable medium used in a design process provides a transmitter having a frequency response controllable in accordance with an operational parameter, and may include a storage operable to store operational parameters for controlling a frequency
8219040 Transmitter bandwidth optimization circuit July 10, 2012
A method is provided for operating a transmitter integrated in a microelectronic element. In a calibration phase, a plurality of operational parameters are stored for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions.
8183920 Variable gain amplifier with reduced power consumption May 22, 2012
A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node i
8077534 Adaptive noise suppression using a noise look-up table December 13, 2011
A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage locat
8051340 System and method for balancing delay of signal communication paths through well voltage adjustm November 1, 2011
A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and
8016482 Method and systems of powering on integrated circuit September 13, 2011
Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a p
7995660 Receiver termination circuit for a high speed direct current (DC) serial link August 9, 2011
A method for matching receiver and transmitter common-mode voltages for a high-speed direct current (DC) serial connection between the receiver and the transmitter includes measuring, at the receiver, a common-mode voltage of the transmitter. The common-mode voltage of the transmitter is
7983368 Systems and arrangements for clock and data recovery in communications July 19, 2011
A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock si
7940846 Test circuit for serial link receiver May 10, 2011
A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current s
7936208 Bias circuit for a MOS device May 3, 2011
A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit
7932774 Structure for intrinsic RC power distribution for noise filtering of analog supplies April 26, 2011
A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable r
7930120 System and circuit for determining data signal jitter via asynchronous sampling April 19, 2011
A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are c
7916820 Systems and arrangements for clock and data recovery in communications March 29, 2011
A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incomi
7898286 Critical path redundant logic for mitigation of hardware across chip variation March 1, 2011
Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arran
7840916 Structure for on-chip electromigration monitoring system November 23, 2010
A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltag
7809054 One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery October 5, 2010
Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a de
7792649 System and circuit for constructing a synchronous signal diagram from asynchronously sampled dat September 7, 2010
A system and circuit for constructing a synchronous signal diagram from asynchronous sampled data provides a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is la
7770139 Design structure for a flexible multimode logic element for use in a configurable mixed-logic si August 3, 2010
A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing conv
7769057 High speed serial link output stage having self adaptation for various impairments August 3, 2010
A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to
7755420 Intrinsic RC power distribution for noise filtering of analog supplies July 13, 2010
Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set
7721134 Method for on-chip diagnostic testing and checking of receiver margins May 18, 2010
A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e.,
7719302 On-chip electromigration monitoring May 18, 2010
A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive commu
7716007 Design structures of powering on integrated circuit May 11, 2010
Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating elemen
7698802 Method for manufacturing a calibration device April 20, 2010
A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism
7684478 Generating an eye diagram of integrated circuit transmitted signals March 23, 2010
A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential time
7661052 Using statistical signatures for testing high-speed circuits February 9, 2010
A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the
7624289 Power network reconfiguration using MEM switches November 24, 2009
A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and
7570071 Impedance calibration for source series terminated serial link transmitter August 4, 2009
Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an imped
7566946 Precision passive circuit structure July 28, 2009
A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements
7541855 CML delay cell with linear rail-to-rail tuning range and constant output swing June 2, 2009
A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a c
7539473 Overshoot reduction in VCO calibration for serial link phase lock loop (PLL) May 26, 2009
A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter
7522000 Design structure for a serial link output stage differential amplifier April 21, 2009
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tol
7512177 Method and apparatus for generating random jitter March 31, 2009
Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase
7511548 Clock distribution network, structure, and method for providing balanced loading in integrated c March 31, 2009
A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits an
7511530 Nodal charge compensation for SST driver having data mux in output stage March 31, 2009
An (SST) driver circuit having additional circuitry for minimizing data-dependent jitter in the SST driver and increasing frequency amplitude in the SST driver. The additional circuity comprises a plurality of switches configured to be turned on or pulsed on momentarily during operat
7501880 Body-biased enhanced precision current mirror March 10, 2009
A body-biased enhanced current mirror circuit is disclosed wherein the body voltage of a current mirror device is adjusted to compensate for the effect of changes in the output voltage on the output current, increasing the output impedance. For each instance of the current mirror, this
7483806 Design structures, method and systems of powering on integrated circuit January 27, 2009
Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating elemen
7479819 Clock distribution network, structure, and method for providing balanced loading in integrated c January 20, 2009
A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits an
7477713 method for providing automatic adaptation to frequency offsets in high speed serial links January 13, 2009
Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compens
7460602 Method for performing high speed serial link output stage having self adaptation for various imp December 2, 2008
A high speed serial link method is provided, using a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value
7449942 Intrinsic RC power distribution for noise filtering of analog supplies November 11, 2008
Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set
7429877 Design structure for a flexible multimode logic element for use in a configurable mixed-logic si September 30, 2008
A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing
7411422 Driver/equalizer with compensation for equalization non-idealities August 12, 2008
A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output o
7405620 Differential amplifier and method July 29, 2008
A method of forming a differential amplifier on a substrate which has a greater tolerance for applied voltages and a chip so formed. The differential amplifier circuit on a substrate has additional transistors connected with resistors which form a voltage divider, thereby sharing the
7404114 System and method for balancing delay of signal communication paths through well voltage adjustm July 22, 2008
A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and
7403057 CML delay cell with linear rail-to-rail tuning range and constant output swing July 22, 2008
A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a c
7403039 Flexible multimode logic element for use in a configurable mixed-logic signal distribution path July 22, 2008
A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limit
7394273 On-chip electromigration monitoring system July 1, 2008
A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has
7391271 Adjustment of PLL bandwidth for jitter control using feedback circuitry June 24, 2008
Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump
7391266 Serial link output stage differential amplifier and method June 24, 2008
Protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exc
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