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Inventor:
Coulson; Andrew R.
Address:
Santa Monica, CA
No. of patents:
4
Patents:












Patent Number Title Of Patent Date Issued
5459340 Adaptive configurable gate array October 17, 1995
A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant
5451801 Adaptive configurable gate array September 19, 1995
A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant
5350704 Method of making adaptive configurable gate array by using a plurality of alignment markers September 27, 1994
A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant
5217916 Method of making an adaptive configurable gate array June 8, 1993
A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant










 
 
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