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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Corbeil, Jr.; John D.
Address:
Fort Collins, CO
No. of patents:
2
Patents:












Patent Number Title Of Patent Date Issued
7406671 Method for performing design rule check of integrated circuit July 29, 2008
The present invention provides a method for performing design rule check (DRC) of an integrated circuit. A design layout of the integrated circuit is provided. The integrated circuit includes a complex circuit. A DRC tool is used to compare a portion of the design layout with a reference
6880142 Method of delay calculation for variation in interconnect metal process April 12, 2005
A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the










 
 
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