| Patent Number |
Title Of Patent |
Date Issued |
| 7599381 |
Scheduling eligible entries using an approximated finish delay identified for an entry based on |
October 6, 2009 |
| Eligible entries are scheduled using an approximated finish delay identified for an entry based on an associated speed group. One implementation maintains schedule entries, each respectively associated with a start time and a speed group. Each speed group is associated with an approx |
| 7573911 |
Method of encoding a data packet |
August 11, 2009 |
| The invention provides a method of encoding a data packet for encapsulation in one or more frames for communication from a transmitter to a receiver in a network interface. The method includes dividing the data packet into one or more data chunks and determining the length of a data |
| 7567508 |
Method and system for providing delay bound and priortized packet dropping |
July 28, 2009 |
| A method and system for providing delay bound and prioritized packet dropping are disclosed. The system limits the size of a queue configured to deliver packets in FIFO order by a threshold based on a specified delay bound. Received packets are queued if the threshold is not exceeded |
| 7551617 |
Multi-threaded packet processing architecture with global packet memory, packet recirculation, a |
June 23, 2009 |
| A network processor has numerous novel features including a multi-threaded processor array, a multi-pass processing model, and Global Packet Memory (GPM) with hardware managed packet storage. These unique features allow the network processor to perform high-touch packet processing at hig |
| 7522609 |
Propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical sch |
April 21, 2009 |
| Methods, apparatus, data structures, computer-readable media, and mechanisms may include or be used with a hierarchy of schedules with propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a p |
| 7500009 |
Rate computations of particular use in scheduling activities or items such as the sending of pac |
March 3, 2009 |
| Rate computations are performed such as for use in scheduling activities, such as, but not limited to packets, processes, traffic flow, etc. One implementation identifies an approximated inverse rate, a fix-up adjustment value, and a quantum. An activity measurement value is maintain |
| 7480308 |
Distributing packets and packets fragments possibly received out of sequence into an expandable |
January 20, 2009 |
| Packets and packets fragments possibly received out of sequence are distributed into an expandable set of queues. For each particular packet or fragment, a queue within a set of queues is identified that does not contain a packet or packet fragment that is subsequent to the particular |
| 7453898 |
Methods and apparatus for simultaneously scheduling multiple priorities of packets |
November 18, 2008 |
| Methods and apparatus are disclosed for simultaneously scheduling multiple priorities of packets, such as in systems having a non-blocking switching fabric. In one implementation, the maximum bandwidth which a particular input can send is identified. During a scheduling cycle, a current |
| 7441101 |
Thread-aware instruction fetching in a multithreaded embedded processor |
October 21, 2008 |
| The present invention provides a multithreaded processor, such as a network processor, that fetches instructions in a pipeline stage based on feedback signals from later stages. The multithreaded processor comprises a pipeline with an instruction unit in the early stage and an instructio |
| 7408937 |
Methods and apparatus for identifying a variable number of items first in sequence from a variab |
August 5, 2008 |
| Methods and apparatus are disclosed for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms, such as, but not limited to the SLIP/I SLIP scheduling algorithms or variants |
| 7360064 |
Thread interleaving in a multithreaded embedded processor |
April 15, 2008 |
| The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication latencies. In an up |
| 7349418 |
Residue-based encoding of packet lengths of particular use in processing and scheduling packets |
March 25, 2008 |
| Processing a packet typically includes enqueuing the packet on to a queue when it arrives at a device, and then at some later time under control of the scheduler, dequeuing the packet for transmission. The scheduler needs some representation of the packet length for its uses when dequeui |
| 7304942 |
Methods and apparatus for maintaining statistic counters and updating a secondary counter storag |
December 4, 2007 |
| Methods and apparatus are disclosed for maintaining statistic counters and updating a secondary counter memory via a queue for reducing or eliminating overflow of the counters. Multiple counter values are stored in a primary counter storage. An indication of a particular counter to u |
| 7080365 |
Method and apparatus for simulation system compiler |
July 18, 2006 |
| A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate f |
| 7043596 |
Method and apparatus for simulation processor |
May 9, 2006 |
| A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first |
| 7036114 |
Method and apparatus for cycle-based computation |
April 25, 2006 |
| A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a pl |
| 6980567 |
Method of encoding a data packet |
December 27, 2005 |
| The invention provides a method of encoding a data packet for encapsulation in one or more frames for communication from a transmitter to a receiver in a network interface. The method includes dividing the data packet into one or more data chunks and determining the length of a data chun |
| 6772299 |
Method and apparatus for caching with variable size locking regions |
August 3, 2004 |
| A method of managing data in a cache memory includes mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines, locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache regio |
| 6556045 |
Digital designs optimized with time division multiple access technology |
April 29, 2003 |
| A system and method for designing a digital circuit. The method includes identifying a single phase digital circuit implementing a desired function and operating at a first rate and determining a number of copies of the single phase digital circuit that are required for the digital circu |
| 6516442 |
Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor syste |
February 4, 2003 |
| A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples |
| 6466825 |
Method and apparatus for address transfers, system serialization, and centralized cache and tran |
October 15, 2002 |
| A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, a |
| 6292705 |
Method and apparatus for address transfers, system serialization, and centralized cache and tran |
September 18, 2001 |
| A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, a |
| 6000006 |
Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile |
December 7, 1999 |
| A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a |
| 5956743 |
Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA |
September 21, 1999 |
| A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correctio |
| 5951702 |
RAM-like test structure superimposed over rows of macrocells with added differential pass transi |
September 14, 1999 |
| A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell h |
| 5822251 |
Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between |
October 13, 1998 |
| A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an a |
| 5784590 |
Slave cache having sub-line valid bits updated by a master cache |
July 21, 1998 |
| A cache system has a large master cache and smaller slave caches. The slave caches are coupled to the processor's pipelines and are kept small and simple to increase their speed. The master cache is set-associative and performs many of the complex cache management operations for the slav |
| 5781457 |
Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectore |
July 14, 1998 |
| A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs bu |
| 5751614 |
Sign-extension merge/mask, rotate/shift, and boolean operations executed in a vectored mux on an |
May 12, 1998 |
| A processor has an execution unit that includes an arithmetic-logic-unit (ALU). Logic instructions are executed by a Boolean logic unit constructed around a 4:1 vectored mux. For Boolean logic instructions, the two operands are applied to the select control inputs of the vectored mux, |
| 5692152 |
Master-slave cache system with de-coupled data and tag pipelines and loop-back |
November 25, 1997 |
| A cache system has a large master cache and smaller slave caches. The slave caches are coupled to the processor's pipelines and are kept small and simple to increase their speed. The master cache is set-associative and performs many of the complex cache management operations for the slav |
| 5644752 |
Combined store queue for a master-slave cache system |
July 1, 1997 |
| A master-slave cache system has a large master cache and smaller slave caches, including a slave data cache for supplying operands to an execution pipeline of a processor. The master cache performs all cache coherency operations, freeing the slaves to supply the processor's pipelines |
| 5633819 |
Inexact leading-one/leading-zero prediction integrated with a floating-point adder |
May 27, 1997 |
| The sum from a floating point adder is normalized by an initial shift based on a prediction for the position of the leading one or zero in the sum. This leading-one/zero prediction is based not on the operands input to the adder, nor the result from the adder, but on the intermediate gen |
| 5608886 |
Block-based branch prediction using a target finder array storing target sub-addresses |
March 4, 1997 |
| A target finder array in the instruction cache contains a lower portion of the target address and a block encoding indicating if the target address is within the same 2K-byte block that the branch instruction is in, or if the target address is in the next or previous 2K-byte block. The u |
| 5598553 |
Program watchpoint checking using paging with sub-page validity |
January 28, 1997 |
| Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is |
| 5574677 |
Adaptive non-restoring integer divide apparatus with integrated overflow detect |
November 12, 1996 |
| The number of steps to perform integer division is reduced by combining detection of a remainder overflow with the final remainder restore step. When the sign bit of the partial remainder flips during the restore step, then there is no remainder overflow. However, when the sign bit does |
| 5551001 |
Master-slave cache system for instruction and data cache memories |
August 27, 1996 |
| A master-slave cache system has a large, set-associative master cache, and two smaller direct-mapped slave caches, a slave instruction cache for supplying instructions to an instruction pipeline of a processor, and a slave data cache for supplying data operands to an execution pipeline o |
| 5542109 |
Address tracking and branch resolution in a processor with multiple execution pipelines and inst |
July 30, 1996 |
| An address of any desired instruction in a super-scalar processor is generated using address tracking logic. A sequential address register in the last stage of the processor's pipelines holds the address of the last or oldest instruction in the pipelines. This register is updated with a |
| 5511017 |
Reduced-modulus address generation using sign-extension and correction |
April 23, 1996 |
| A mixed-modulo address generation unit has several inputs, preferably three. The unit can effectively add together a subset of these inputs in a reduced modulus, and simultaneously add this partial sum to a full-width input using a full modulus, the full modulus being greater than the |
| 5497341 |
Sign-extension of immediate constants in an ALU using an adder in an integer logic unit |
March 5, 1996 |
| An arithmetic-logic unit (ALU) includes a Boolean logic unit and an integer logic unit, both of which are adapted to incorporate the sign extension function for immediate constants or reduced-width operands. The Boolean logic unit is constructed from 4:1 multiplexers (muxes), one mux for |
| 5442577 |
Sign-extension of immediate constants in an alu |
August 15, 1995 |
| An arithmetic-logic unit (ALU) includes a Boolean logic unit and an integer logic unit, both of which are adapted to incorporate the sign extension function for immediate constants or reduced-width operands. The Boolean logic unit is constructed from 4:1 multiplexers (muxes), one mux for |
| 5440710 |
Emulation of segment bounds checking using paging with sub-page validity |
August 8, 1995 |
| Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is |
