| Patent Number |
Title Of Patent |
Date Issued |
| 7456099 |
Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices |
November 25, 2008 |
| A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between t |
| 7439172 |
Circuit structure with low dielectric constant regions and method of forming same |
October 21, 2008 |
| A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is |
| 7402532 |
Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer |
July 22, 2008 |
| An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorp |
| 7402463 |
Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse |
July 22, 2008 |
| An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of lea |
| 7397260 |
Structure and method for monitoring stress-induced degradation of conductive interconnects |
July 8, 2008 |
| A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting lin |
| 7397081 |
Sidewall semiconductor transistors |
July 8, 2008 |
| A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconducto |
| 7335588 |
Interconnect structure and method of fabrication of same |
February 26, 2008 |
| A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the |
| 7282802 |
Modified via bottom structure for reliability enhancement |
October 16, 2007 |
| The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The |
| 7224021 |
MOSFET with high angle sidewall gate and contacts for reduced miller capacitance |
May 29, 2007 |
| The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0.degree. and not more than about 45.degree.. In suc |
| 7223691 |
Method of forming low resistance and reliable via in inter-level dielectric interconnect |
May 29, 2007 |
| A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, |
| 7223654 |
MIM capacitor and method of fabricating same |
May 29, 2007 |
| A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate |
| 7214608 |
Interlevel dielectric layer and metal layer sealing |
May 8, 2007 |
| Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner in |
| 7187085 |
Semiconductor device including dual damascene interconnections |
March 6, 2007 |
| A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substr |
| 7166913 |
Heat dissipation for heat generating element of semiconductor device and related method |
January 23, 2007 |
| A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting pa |
| 7122898 |
Electrical programmable metal resistor |
October 17, 2006 |
| The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is |
| 7122462 |
Back end interconnect with a shaped interface |
October 17, 2006 |
| An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and |
| 7115921 |
Nano-scaled gate structure with self-interconnect capabilities |
October 3, 2006 |
| Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate co |
| 7112502 |
Method to fabricate passive components using conductive polymer |
September 26, 2006 |
| A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices c |
| 7105445 |
Interconnect structures with encasing cap and methods of making thereof |
September 12, 2006 |
| A method of making an interconnect which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric and depositing an encasing cap over the |
| 7102232 |
Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer |
September 5, 2006 |
| An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorp |
| 7101784 |
Method to generate porous organic dielectric |
September 5, 2006 |
| The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. |
| 7092235 |
Method for adjusting capacitance of an on-chip capacitor |
August 15, 2006 |
| A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam inclu |
| 7088074 |
System level device for battery and integrated circuit integration |
August 8, 2006 |
| A system level device for battery and integrated circuit chip integration comprises at least one battery; at least one integrated circuit chip powered by the at least one battery; and a package connected to any of the at least one battery and the at least one integrated circuit chip, |
| 7041552 |
Integrated metal-insulator-metal capacitor and metal gate transistor |
May 9, 2006 |
| An integrated circuit structure is disclosed that comprises a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each o |
| 7041525 |
Three-dimensional island pixel photo-sensor |
May 9, 2006 |
| A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, |
| 7001835 |
Crystallographic modification of hard mask properties |
February 21, 2006 |
| A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 .mu.Ohm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks |
| 6967416 |
Shared on-chip decoupling capacitor and heat-sink devices |
November 22, 2005 |
| A method and structure for an integrated chip structure comprises a substrate having a power supply, a chip attached to the substrate, at least two decoupling capacitors attached to the chip and to the power supply, and a control circuit adapted to select physical locations of active |
| 6964892 |
N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same |
November 15, 2005 |
| An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration implantation, and an N-driver coupled to the boost gate stack. |
| 6958522 |
Method to fabricate passive components using conductive polymer |
October 25, 2005 |
| A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices c |
| 6933189 |
Integration system via metal oxide conversion |
August 23, 2005 |
| A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a |
| 6921978 |
Method to generate porous organic dielectric |
July 26, 2005 |
| The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The |
| 6916729 |
Salicide formation method |
July 12, 2005 |
| A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-no |
| 6911354 |
Polymer thin-film transistor with contact etch stops |
June 28, 2005 |
| A method and structure of forming a vertical polymer transistor structure is disclosed having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconduc |
| 6909145 |
Metal spacer gate for CMOS FET |
June 21, 2005 |
| A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilicon gate conductor over |
| 6870263 |
Device interconnection |
March 22, 2005 |
| A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electr |
| 6869895 |
Method for adjusting capacitance of an on-chip capacitor |
March 22, 2005 |
| A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material. |
| 6864504 |
Planar polymer transistor |
March 8, 2005 |
| A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistor is made with all organic materials. The gate |
| 6794721 |
Integration system via metal oxide conversion |
September 21, 2004 |
| A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a |
| 6787836 |
Integrated metal-insulator-metal capacitor and metal gate transistor |
September 7, 2004 |
| An integrated circuit structure is disclosed that comprises a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each o |
| 6777761 |
Semiconductor chip using both polysilicon and metal gate devices |
August 17, 2004 |
| A semiconductor structure (and method for forming) having transistors having both metal gates and polysilicon gates on a single substrate in a single process is disclosed. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. Th |
| 6768063 |
Structure and method for shadow mask electrode |
July 27, 2004 |
| A method and structure for an electrode device, whereby a second electrode is deposited on a first electrode such that there is an increase in the capacitive coupling between the pair of conductive electrodes. The electrodes are self-aligning such that the patterning manufacturing pr |
| 6759332 |
Method for producing dual damascene interconnections and structure produced thereby |
July 6, 2004 |
| A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, |
| 6743670 |
High dielectric constant materials forming components of DRAM such as deep-trench capacitors and |
June 1, 2004 |
| A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions |
| 6733602 |
Polycrystalline material with surface features projecting from a surface thereof |
May 11, 2004 |
| A method of forming extruded structures from a polycrystalline material and structures formed thereby. The method generally entails forming a structure that comprises a polycrystalline material constrained by a second material in all but one direction, with the polycrystalline materi |
| 6720602 |
Dynamic random access memory (DRAM) cell with folded bitline vertical transistor and method of p |
April 13, 2004 |
| A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating |
| 6720595 |
Three-dimensional island pixel photo-sensor |
April 13, 2004 |
| A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, t |
| 6696759 |
Semiconductor device with diamond-like carbon layer as a polish-stop layer |
February 24, 2004 |
| A semiconductor structure includes a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate in a damascene process flow. The semiconductor structure includes a substrate having a dielectric layer followed by the diamond-like c |
| 6664576 |
Polymer thin-film transistor with contact etch stops |
December 16, 2003 |
| A method and structure of forming a vertical polymer transistor structure is disclosed having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconduc |
| 6652956 |
X-ray printing personalization technique |
November 25, 2003 |
| A method and structure to form a conductive pattern on a ceramic sheet deposits a photosensitive conductive material on a carrier and exposes a pattern of x-ray energy on the material and sinters the carrier and the material to the ceramic sheet so that only the conductive pattern of the |
| 6638681 |
X-ray printing personalization technique |
October 28, 2003 |
| A method and structure to form a conductive pattern on a ceramic sheet deposits a photosensitive conductive material on a carrier and exposes a pattern of x-ray energy on the material and sinters the carrier and the material to the ceramic sheet so that only the conductive pattern of the |
