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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Church; Michael D.
Address:
Sebastian, FL
No. of patents:
19
Patents:












Patent Number Title Of Patent Date Issued
8274160 Active area bonding compatible high current structures September 25, 2012
A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the c
8268693 Method for fabricating a radiation hardened device September 18, 2012
A "tabbed" MOS device provides radiation hardness while supporting reduced gate width requirements. The "tabbed" MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the "tabbed" MOS device is designed such that a width of the tab is
8000139 Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a gener August 16, 2011
A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain
7944745 Flash memory array of floating gate-based non-volatile memory cells May 17, 2011
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A
7903465 Memory array of floating gate-based non-volatile memory cells March 8, 2011
A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically
7804143 Radiation hardened device September 28, 2010
A "tabbed" MOS device provides radiation hardness while supporting reduced gate width requirements. The "tabbed" MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the "tabbed" MOS device is designed such that a width of the tab is base
7795130 Active area bonding compatible high current structures September 14, 2010
A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the c
7709907 ESD structure May 4, 2010
An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and
7688627 Flash memory array of floating gate-based non-volatile memory cells March 30, 2010
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A
7224074 Active area bonding compatible high current structures May 29, 2007
An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad an
7005369 Active area bonding compatible high current structures February 28, 2006
An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad an
6812108 BICMOS process with low temperature coefficient resistor (TCRL) November 2, 2004
A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for
6798024 BiCMOS process with low temperature coefficient resistor (TCRL) September 28, 2004
A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for
6350640 CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxilia February 26, 2002
To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CM
6329260 Analog-to-digital converter and method of fabrication December 11, 2001
An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.
5994755 Analog-to-digital converter and method of fabrication November 30, 1999
An integrated circuit has a pseudosubstrate 6060 with an isolation moat 9505. Substrate 6001 has one conductivity and a subcircuit region 6060 has an opposite conductivity. Digital CMOS devices are formed in the subcircuit over region 6060 and operate between zero to +5 volts. Analog
5817564 Double diffused MOS device and method October 6, 1998
The double lightly diffused transistor has drain regions with a lightly doped arsenic region 42 entirely contained within a lightly doped phosphorus region 40. The arsenic region is implanted with a dose less than 1.times.10.sup.15 ions/cm.sup.2 and is preferably implanted with a dos
5481129 Analog-to-digital converter January 2, 1996
A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog
5416351 Electrostatic discharge protection May 16, 1995
An ESD protection diode for a CMOS or BiCMOS integrated circuit formed by imbedding a Zener diode in the drain of a MOS device used as a protection diode. The Zener diode may be formed with the preexisting process steps of a BiCMOS process, and it provides a low voltage trigger for avala










 
 
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