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Inventor: Chung; Jiyoon
Address: South Burlington, VT
No. of patents: 1
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 7199625 |
Delay locked loop structure providing first and second locked clock signals |
April 3, 2007 |
| A delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto the clock signal and provide a first locked clock signal over a first frequency range and a second locked clock signal over a |
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