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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chung; Henry
Address:
Singapore, SG
No. of patents:
3
Patents:












Patent Number Title Of Patent Date Issued
6063702 Global planarization method for inter level dielectric layers using IDL blocks May 16, 2000
The present invention provides a method of manufacturing of planarizing an insulating layer using a reduced size reversed interconnect mask and an etch stop layer. Spaced interconnections 22 are provided over the semiconductor substrate 10. An etch stop layer 26 is formed over the ra
6037253 Method for increasing interconnect packing density in integrated circuits March 14, 2000
The present invention provides a method of forming closely spaced interconnections over a semiconductor structure using conventional photolithographic and etching methods and tools. The process which begins by providing an insulating layer 14 over a semiconductor structure 10. A cond
5792707 Global planarization method for inter level dielectric layers of integrated circuits August 11, 1998
The present invention provides a method of manufacturing of planarizing an insulating layer using a sized reversed interconnect mask and two polish stop layers. Spaced interconnections 14 are provided over the semiconductor substrate 10. An insulating layer 22 is formed over the inte










 
 
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