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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chung; Dae-Hyun
Address:
Daejeon, KR
No. of patents:
5
Patents:












Patent Number Title Of Patent Date Issued
8004328 AC-coupling phase interpolator and delay-locked loop using the same August 23, 2011
An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it
7778097 AC coupling circuits including resistive feedback and related methods and devices August 17, 2010
An integrated circuit device may include an amplifier having an amplifier input configured to receive an input signal with the amplifier being configured to provide an amplifier output signal at an amplifier output responsive to the input signal received at the amplifier input. A cap
7737748 Level shifter of semiconductor device and method for controlling duty ratio in the device June 15, 2010
A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground vo
6987407 Delay locked loops having delay time compensation and methods for compensating for delay time of January 17, 2006
A delay locked loop (DLL) is provided that includes a phase detector configured to detect a phase error between an internal clock signal and the external clock signal and output a phase error signal. A low pass filter is configured to output a predetermined control signal in response
6920080 Methods for generating output control signals in synchronous semiconductor memory devices and re July 19, 2005
A synchronous semiconductor memory device includes an output control signal generating circuit that generates a data output control signal in response to an internal clock signal, an output control clock signal and a CAS latency signal. The output control signal generating circuit succes










 
 
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