| Patent Number |
Title Of Patent |
Date Issued |
| 7595657 |
Dynamic dual control on-die termination |
September 29, 2009 |
| Controlling on-die termination on a bi-directional single-ended data bus carrying data between a controller and a memory device. The controller and the memory device respectively include input termination pull-ups and input termination pull-downs. An enabled state is maintained for the |
| 7389457 |
Shift registers free of timing race boundary scan registers with two-phase clock control |
June 17, 2008 |
| A chain of boundary scan registers is configured to use a two-phase clock signal to avoid data timing race conditions. The two-phase clock signal is generated according to a two-phase clock generator, which includes two self-timed clock pulse generators for each boundary scan register. T |
| 7313040 |
Dynamic sense amplifier for SRAM |
December 25, 2007 |
| A dynamic sense amplifier for static random access memory (SRAM) is provided. The dynamic sense amplifier includes a pre-amplifier configured to amplify small input signals according to a first clock signal, and a main sense-latch coupled to the pre-amplifier, wherein the main sense- |
| 5121013 |
Noise reducing output buffer circuit with feedback path |
June 9, 1992 |
| Electrical buffer output circuitry includes a first high branch having a high signal input terminal, a low input branch having a low input signal input terminal, and a signal output for the buffer circuitry. Either the high branch or the low branch is turned on in response to a signal at |
| 4928260 |
Content addressable memory array with priority encoder |
May 22, 1990 |
| A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a p |
| 4890260 |
Content addressable memory array with maskable and resettable bits |
December 26, 1989 |
| A content addressable memory array includes an array of M words containing bits configured in N bits for each word. One of the bits in each of the words is a settable skip bit, and during a search of the memory array, the array is examined to detect the presence therein of skip bits. If |
| 4888731 |
Content addressable memory array system with multiplexed status and command information |
December 19, 1989 |
| A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the |
| 4634894 |
Low power CMOS reference generator with low impedance driver |
January 6, 1987 |
| A low power, low output impedance, CMOS voltage reference with high source/sink current driving capability. A CMOS current mirror preamplifier includes matched transistor pairs having their W/L ratios scaled to reduce the level of current to the subthreshold region. A CMOS source followe |
| 4615020 |
Nonvolatile dynamic ram circuit |
September 30, 1986 |
| A nonvolatile dynamic RAM capable of operating in a dynamic RAM mode and a second, nonvolatile mode, is disclosed. The nonvolatile dynamic RAM has a memory cell having a transfer transistor for coupling a storage capacitor having a floating gate to a bit line. The memory cell holds infor |
| 4611309 |
Non-volatile dynamic RAM cell |
September 9, 1986 |
| A non-volatile dynamic RAM circuit where each memory cell includes an access transistor, a floating gate structure, and a recall transistor connected in series between an I/O bit line and a common line. A conducting plate and storage node of the floating gate structure functions as t |
| 4598387 |
Capacitive memory signal doubler cell |
July 1, 1986 |
| A plurality of capacitive memory elements are coupled between two pairs of bit line and return line halves. A cross-coupled MOSFET sense amplifier, configured to operate in a race mode, connects between the two bit line/return line pairs. The return line of each bit line/return line pair |
| 4438346 |
Regulated substrate bias generator for random access memory |
March 20, 1984 |
| An improved substrate bias generator is disclosed for use in a capacitive charge storage integrated circuit memory device having an external voltage supply. The generator comprises means for generating first and second timing signals, charge pumping means disposed for pumping positive ch |
| 4421996 |
Sense amplification scheme for random access memory |
December 20, 1983 |
| In source-clocked type of cross-coupled latch sense amplifier of a dynamic random access memory device, there is provided a sense clock that employs multiple extended dummy memory cells to provide reference timing which tracks time constants of word line, cell transfer gate, cell capacit |
