| Patent Number |
Title Of Patent |
Date Issued |
| 7339398 |
Driver impedance control apparatus and system |
March 4, 2008 |
| A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down array, a pull-up arra |
| 7282953 |
Pre-buffer level shifter and input/output buffer apparatus |
October 16, 2007 |
| A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transisto |
| 7050282 |
Power supply clamp circuit |
May 23, 2006 |
| A power supply clamp circuit for preventing damage to an integrated circuit due to electrostatic discharge. The power supply clamp circuit includes a voltage generator electrically connected to a first node for generating a voltage; a first PMOS transistor having a source electricall |
| 6728086 |
Power-rail electrostatic discharge protection circuit with a dual trigger design |
April 27, 2004 |
| A power-rail ESD (electrostatic discharge) protection circuit with a dual trigger design is proposed, which is coupled between a first power line and a second power line connected to an IC device for protecting the IC device against ESD on the first power line and the second power line. |
| 6690561 |
Effective gate-driven or gate-coupled ESD protection circuit |
February 10, 2004 |
| An ESD protection circuit, arranged between a first and second potential terminals, has a RC branch, a voltage adjuster circuit, and an ESD discharge transistor. The RC branch includes a resistor and a capacitor series connected from the first to the second potential terminal. The vo |
| 6690557 |
CMOS whole chip low capacitance ESD protection circuit |
February 10, 2004 |
| A low capacitance electrostatic discharge circuit (ESD) for a built-in CMOS chip capable of protecting an internal circuit within the chip. A first voltage source and a second voltage source are provided to the electrostatic protection circuit. The ESD circuit is coupled to a bonding |
| 6639772 |
Electrostatic discharge protection circuit for protecting input and output buffer |
October 28, 2003 |
| An electrostatic discharge (ESD) protection circuit for protecting input and output buffers. The ESD protection circuit is driven by a first voltage source and a second voltage source and coupled to a bonding pad. The ESD protection circuit has a first resistor, a first PMOS transistor, |
