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Choi; Young-Joon
Gyeonggi-do, KR
No. of patents:

Patent Number Title Of Patent Date Issued
8286021 Flash memory devices with high data transmission rates and memory systems including such flash m October 9, 2012
A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to
8117374 Flash memory control devices that support multiple memory mapping schemes and methods of operati February 14, 2012
There is provided an apparatus for controlling a flash memory, which includes a memory for storing a plurality of flash translation layers; and a control block for, when an access is requested from outside, determining a pattern of the access, selecting one of the flash translation l
8001356 Methods and apparatus for reallocating addressable spaces within memory devices August 16, 2011
Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable s
7110301 Non-volatile semiconductor memory device and multi-block erase method thereof September 19, 2006
A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing t
7085167 Methods for programming user data and confirmation information in nonvolatile memory devices August 1, 2006
Method of programming nonvolatile memory devices are provided in which data is programmed into a first plurality of memory cells of the nonvolatile memory device. At the same time associated programming confirmation information is programmed into at least one second memory cell of th

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