| Patent Number |
Title Of Patent |
Date Issued |
| RE36490 |
Power and signal line bussing method for memory devices |
January 11, 2000 |
| A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is |
| 7232717 |
Method of manufacturing non-volatile DRAM |
June 19, 2007 |
| A method of forming a non-volatile DRAM includes, in part: forming p-well and an n-well between two trench isolation regions formed in a semiconductor substrate, forming a polysilicon control gate of the non-volatile device disposed in the non-volatile DRAM, forming a first oxide spa |
| 7186612 |
Non-volatile DRAM and a method of making thereof |
March 6, 2007 |
| A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide |
| 6972229 |
Method of manufacturing self-aligned non-volatile memory device |
December 6, 2005 |
| A method of forming a self-aligned non-volatile device, includes, in part: forming trench isolation regions, forming a well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first |
| 6965524 |
Non-volatile static random access memory |
November 15, 2005 |
| In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to the SRAM cell. The memory cell may be adapted to operate differentially if a second SR |
| 6965145 |
Non-volatile memory device |
November 15, 2005 |
| A non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of th |
| 6954377 |
Non-volatile differential dynamic random access memory |
October 11, 2005 |
| In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated |
| 6806148 |
Method of manufacturing non-volatile memory device |
October 19, 2004 |
| A method of forming an integrated circuit, includes, in part: forming trench isolation in a semiconductor substrate, forming a first well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, fo |
| 6798008 |
Non-volatile dynamic random access memory |
September 28, 2004 |
| In accordance with the present invention, a memory cell includes a non-volatile device and a DRAM cell. The DRAM cell further includes an MOS transistor and a capacitor. The non-volatile device include a control gate region and a guiding gate region that may partially overlap. The no |
| 6514819 |
High capacity stacked DRAM device and process for making a smaller geometry |
February 4, 2003 |
| A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow widths down to 1000A and small spa |
| 5946566 |
Method of making a smaller geometry high capacity stacked DRAM device |
August 31, 1999 |
| A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow widths down to 1000 .ANG. and smal |
