| Patent Number |
Title Of Patent |
Date Issued |
| 7569499 |
Semiconductor device made by multiple anneal of stress inducing layer |
August 4, 2009 |
| The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises forming a stress inducing layer over a semiconductor substrate, subjecting the stress inducing layer to a first temperature anneal, and subjecting the semiconductor substrate to a |
| 7553718 |
Methods, systems and structures for forming semiconductor structures incorporating high-temperat |
June 30, 2009 |
| A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embod |
| 7553717 |
Recess etch for epitaxial SiGe |
June 30, 2009 |
| A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ re |
| 7348232 |
Highly activated carbon selective epitaxial process for CMOS |
March 25, 2008 |
| In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and forming a first recess i |
| 7202537 |
Versatile system for limiting electric field degradation of semiconductor structures |
April 10, 2007 |
| The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) |
| 7129127 |
Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation |
October 31, 2006 |
| A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown |
| 7112516 |
Fabrication of abrupt ultra-shallow junctions |
September 26, 2006 |
| One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, s |
| 6852603 |
Fabrication of abrupt ultra-shallow junctions |
February 8, 2005 |
| One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, s |
| 6849528 |
Fabrication of ultra shallow junctions from a solid source with fluorine implantation |
February 1, 2005 |
| One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, s |
