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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chevallier; Christophe J.
Address:
Palo Alto, CA
No. of patents:
171
Patents:


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Patent Number Title Of Patent Date Issued
8130549 Apparatus and method for detecting over-programming condition in multistate memory device March 6, 2012
A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the
8089542 CMOS imager with integrated circuitry January 3, 2012
A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral circuitry allows for a single chip image sensing device.
8062942 Method for fabricating multi-resistive state memory devices November 22, 2011
A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive ele
7995371 Threshold device for a memory array August 9, 2011
A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the firs
7952631 CMOS imager with integrated circuitry May 31, 2011
A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral circuitry allows for a single chip image sensing device.
7898841 Preservation circuit and methods to maintain values representing data in one or more layers of m March 1, 2011
Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain st
7884349 Selection device for re-writable memory February 8, 2011
A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across th
7830701 Contemporaneous margin verification and memory access for memory cells in cross point memory arr November 9, 2010
Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array.
7719876 Preservation circuit and methods to maintain values representing data in one or more layers of m May 18, 2010
Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain st
7701791 Low read current architecture for memory April 20, 2010
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
7633790 Multi-resistive state memory device with conductive oxide electrodes December 15, 2009
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electr
7569414 CMOS imager with integrated non-volatile memory August 4, 2009
A CMOS imager and non-volatile memory are integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. A protective layer covers the non-volatile memory contained on the substrate for blocking lig
7505347 Method for sensing a signal in a two-terminal memory array having leakage current March 17, 2009
A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total curre
7457997 Apparatus and method for detecting over-programming condition in multistate memory device November 25, 2008
An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programme
7457147 Two terminal memory array having reference cells November 25, 2008
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7437647 Mode entry circuit and method October 14, 2008
An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference voltages by a voltage margin.
7436723 Method for two-cycle sensing in a two-terminal memory array having leakage current October 14, 2008
A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total curre
7382645 Two terminal memory array having reference cells June 3, 2008
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7382644 Two terminal memory array having reference cells June 3, 2008
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7327601 Providing a reference voltage to a cross point memory array February 5, 2008
Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array. The peripheral circuitry can be activated before, after or during selection
7251187 Memory system, method and predecoding circuit operable in different modes for selectively access July 31, 2007
A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a numbe
7248515 Non-volatile memory with test rows for disturb detection July 24, 2007
A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test r
7236400 Erase verify for non-volatile memory using a bitline current-to-voltage converter June 26, 2007
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predet
7236399 Method for erase-verifying a non-volatile memory capable of identifying over-erased and under-er June 26, 2007
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predet
7230855 Erase verify for non-volatile memory using bitline/reference current-to-voltage converters June 12, 2007
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predet
7227775 Two terminal memory array having reference cells June 5, 2007
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7227767 Cross point memory array with fast access time June 5, 2007
Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if th
7196934 Non-volatile memory with erase verify circuit having comparators indicating under-erasure, erasu March 27, 2007
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predet
7167396 Erase verify for nonvolatile memory using reference current-to-voltage converters January 23, 2007
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predet
7133323 Memory system, method and predecoding circuit operable in different modes for selectively access November 7, 2006
A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a numbe
7130239 Memory system, method and predecoding circuit operable in different modes for selectively access October 31, 2006
A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a numbe
7123516 Erase verify for nonvolatile memory using bitline/reference current-to-voltage converters October 17, 2006
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predet
7123513 Erase verify for non-volatile memory using a reference current-to-voltage converter October 17, 2006
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predet
7079442 Layout of driver sets in a cross point memory array July 18, 2006
Layouts of driver sets in a cross point memory array. Since both terminals of a memory cell in a cross point structure are typically used for selection purposes, dedicated driver sets are typically required for both x and y directions. By fabricating the cross point array above the drive
7075817 Two terminal memory array having reference cells July 11, 2006
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7071008 Multi-resistive state material that uses dopants July 4, 2006
A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally dop
7067862 Conductive memory device with conductive oxide electrodes June 27, 2006
A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a
7057935 Erase verify for non-volatile memory June 6, 2006
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predet
7057914 Cross point memory array with fast access time June 6, 2006
Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if th
7054198 Flash memory with fast boot block access May 30, 2006
A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to supply a word line voltage to the remaining memory blocks. The memory device can be operated
7042035 Memory array with high temperature wiring May 9, 2006
A memory array with components that can withstand high temperature fabrication is provided. Some memory materials require high temperature process steps in order to achieve desired properties. During fabrication, a memory material is deposited on structures that may include metal lines
7038935 2-terminal trapped charge memory device with voltage switchable multi-level resistance May 2, 2006
A 2-terminal trapped charge memory device is disclosed with voltage switchable multi-level resistance. The trapped charge memory device has a trapped charge memory body sandwiched between two electrodes. The trapped charge memory body can be made of a variety of semiconducting or ins
7020012 Cross point array using distinct voltages March 28, 2006
Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally,
7009909 Line drivers that use minimal metal layers March 7, 2006
Line drivers that use minimal metal layers. Line driver connections typically need to be made to various other peripheral circuits. Although multiple metal layers could be used to make all the necessary connections, it is desirable to use the fewest metal layers possible. By keeping
7009235 Conductive memory stack with non-uniform width March 7, 2006
A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has
6999363 Non-volatile memory with test rows for disturb detection February 14, 2006
A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test r
6972985 Memory element having islands December 6, 2005
A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are
6970375 Providing a reference voltage to a cross point memory array November 29, 2005
Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array in order to prevent unselected conductive array lines from floating to an undes
6961805 Memory system, method and predecoding circuit operable in different modes for selectively access November 1, 2005
A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a numbe
6954400 Memory system, method and predecoding circuit operable in different modes for selectively access October 11, 2005
A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a numbe
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