| Patent Number |
Title Of Patent |
Date Issued |
| 7220985 |
Self aligned memory element and wordline |
May 22, 2007 |
| An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top |
| 7015504 |
Sidewall formation for high density polymer memory element array |
March 21, 2006 |
| Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side |
| 6989563 |
Flash memory cell with UV protective layer |
January 24, 2006 |
| A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric fl |
| 6955939 |
Memory element formation with photosensitive polymer dielectric |
October 18, 2005 |
| A method of making organic memory devices containing organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The organic memory devices are made using a patternable, photosensitive dielectric that facilitates formation of |
| 6900488 |
Multi-cell organic memory element and methods of operating and fabricating |
May 31, 2005 |
| The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of th |
| 6836398 |
System and method of forming a passive layer by a CMP process |
December 28, 2004 |
| The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is p |
| 6803267 |
Silicon containing material for patterning polymeric memory element |
October 12, 2004 |
| The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, a |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6350639 |
Simplified graded LDD transistor using controlled polysilicon gate profile |
February 26, 2002 |
| An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning |
| 6287922 |
Method for fabricating graded LDD transistor using controlled polysilicon gate profile |
September 11, 2001 |
| An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer, formi |
| 6274443 |
Simplified graded LDD transistor using controlled polysilicon gate profile |
August 14, 2001 |
| An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; formi |
| 6191044 |
Method for forming graded LDD transistor using controlled polysilicon gate profile |
February 20, 2001 |
| An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon la |
| 6013570 |
LDD transistor using novel gate trim technique |
January 11, 2000 |
| An ultra-large scale MOS integrated circuit semiconductor device is processed after the formation of the gate oxide and polysilicon layer by forming a forming a first mask layer over the polysilicon layer followed by a second mask layer over the first mask layer. The first mask layer and |
