| Patent Number |
Title Of Patent |
Date Issued |
| 6870397 |
Input/output circuit with user programmable functions |
March 22, 2005 |
| The I/O circuit of the present invention provides optimal flexibility and performance using a number of different structures and methods. The present invention provides a signal follower circuit for an input pad. In one embodiment, the output buffer is capable of injecting a constant ont |
| 6624656 |
Input/output circuit with user programmable functions |
September 23, 2003 |
| The I/O circuit of the present invention provides optimal flexibility and performance using a number of different structures and methods. The present invention provides a signal follower circuit for an input pad. In one embodiment, the output buffer is capable of injecting a constant ont |
| 6181158 |
Configuration logic to eliminate signal contention during reconfiguration |
January 30, 2001 |
| A structure for providing clearing/programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flo |
| 5770951 |
Configuration logic to eliminate signal contention during reconfiguration |
June 23, 1998 |
| A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programming the memory cells one set at a time, either in a first direction or a second direction. A struct |
| 5631577 |
Synchronous dual port RAM |
May 20, 1997 |
| A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, |
| 5592105 |
Configuration logic to eliminate signal contention during reconfiguration |
January 7, 1997 |
| A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structu |
| 5566123 |
Synchronous dual port ram |
October 15, 1996 |
| A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, |
| 5523963 |
Logic structure and circuit for fast carry |
June 4, 1996 |
| Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the ca |
| 5295090 |
Logic structure and circuit for fast carry |
March 15, 1994 |
| Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the ca |
| 5267187 |
Logic structure and circuit for fast carry |
November 30, 1993 |
| Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the ca |
